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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-04 13:17:15 +0200 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-28 10:13:05 +0000 |
| commit | 64b3a741f558c9fcfe70d27d74fe2c25d96770d7 (patch) | |
| tree | 4f2f525b61ab5de3d69078e2c2a8384a4febd803 /src/dev/intel_8254_timer.cc | |
| parent | 7a6183aa6162419912daa5647d13f030ab0904e2 (diff) | |
| download | gem5-64b3a741f558c9fcfe70d27d74fe2c25d96770d7.tar.xz | |
arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
Writing a 1 to the Overflow Flag Status register should trigger an
interrupt raise/clear depending on the register we are currently using
(PMOVSCLR for clearing and PMOVSSET for raising).
Change-Id: I2091456685a245712045cf7a4932ac36b7dded1d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12531
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/intel_8254_timer.cc')
0 files changed, 0 insertions, 0 deletions