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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-24 11:43:53 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-24 11:43:53 -0500 |
commit | 1031b824b975cec999c37cabc8c05c485a4ae5ca (patch) | |
tree | 18af5987accd59781642001849908ddb486d069a /src/dev/io_device.hh | |
parent | 9f07d2ce7ecf435b9a1946f15fb3491bb4636637 (diff) | |
download | gem5-1031b824b975cec999c37cabc8c05c485a4ae5ca.tar.xz |
MEM: Move port creation to the memory object(s) construction
This patch moves all port creation from the getPort method to be
consistently done in the MemObject's constructor. This is possible
thanks to the Swig interface passing the length of the vector ports.
Previously there was a mix of: 1) creating the ports as members (at
object construction time) and using getPort for the name resolution,
or 2) dynamically creating the ports in the getPort call. This is now
uniform. Furthermore, objects that would not be complete without a
port have these ports as members rather than having pointers to
dynamically allocated ports.
This patch also enables an elaboration-time enumeration of all the
ports in the system which can be used to determine the masterId.
Diffstat (limited to 'src/dev/io_device.hh')
-rw-r--r-- | src/dev/io_device.hh | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index c5f6958ee..d7ed93805 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -192,7 +192,7 @@ class PioDevice : public MemObject /** The pioPort that handles the requests for us and provides us requests * that it sees. */ - PioPort *pioPort; + PioPort pioPort; /** * Every PIO device is obliged to provide an implementation that @@ -271,7 +271,7 @@ class BasicPioDevice : public PioDevice class DmaDevice : public PioDevice { protected: - DmaPort *dmaPort; + DmaPort dmaPort; public: typedef DmaDeviceParams Params; @@ -284,21 +284,25 @@ class DmaDevice : public PioDevice return dynamic_cast<const Params *>(_params); } - void dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay = 0) + void dmaWrite(Addr addr, int size, Event *event, uint8_t *data, + Tick delay = 0) { - dmaPort->dmaAction(MemCmd::WriteReq, addr, size, event, data, delay); + dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay); } - void dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay = 0) + void dmaRead(Addr addr, int size, Event *event, uint8_t *data, + Tick delay = 0) { - dmaPort->dmaAction(MemCmd::ReadReq, addr, size, event, data, delay); + dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay); } - bool dmaPending() { return dmaPort->dmaPending(); } + bool dmaPending() { return dmaPort.dmaPending(); } + + virtual void init(); virtual unsigned int drain(Event *de); - unsigned cacheBlockSize() const { return dmaPort->cacheBlockSize(); } + unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); } virtual Port *getPort(const std::string &if_name, int idx = -1); |