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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-11 13:21:03 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 08:28:51 +0000 |
| commit | 4439c58688af517772c1a1b7f8844e629c51ec11 (patch) | |
| tree | 4a856ebe725ada12f27718e2b202b5fb4a1347dc /src/dev/io_device.hh | |
| parent | 8b3c5309dff79402f7f96660a6d19e450a45356b (diff) | |
| download | gem5-4439c58688af517772c1a1b7f8844e629c51ec11.tar.xz | |
dev-arm: Create postFiq events for GICv2
GICv2 is signaling IRQs only to the CPU. This patch is adding the
capability of scheduling FIQs.
Change-Id: I395afc83eb8d58cfd32cd93372bcb6f804364ef5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12947
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/io_device.hh')
0 files changed, 0 insertions, 0 deletions