diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-11 13:39:00 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 08:28:51 +0000 |
| commit | 721ea8bb83d9c16656c692d32ab9a15ea4dc76d3 (patch) | |
| tree | 9ae1ce10658d3c4c82a0e9b9ffa1f6c0e0f39d07 /src/dev/isa_fake.cc | |
| parent | 4439c58688af517772c1a1b7f8844e629c51ec11 (diff) | |
| download | gem5-721ea8bb83d9c16656c692d32ab9a15ea4dc76d3.tar.xz | |
dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2
Change-Id: Iafaf26344a26eade60c08dd2c0d716af14d9b328
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12948
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/isa_fake.cc')
0 files changed, 0 insertions, 0 deletions