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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-20 13:53:39 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 11:53:49 +0000 |
| commit | 51022bfe0eeaef5f08d6ace98ebfb1917d1b3331 (patch) | |
| tree | 1f25bf357a5527834c9189fb9e33f7ecfd802b77 /src/dev/isa_fake.hh | |
| parent | 7a1f018ce77e5c1b56c241d4899aa454fc168366 (diff) | |
| download | gem5-51022bfe0eeaef5f08d6ace98ebfb1917d1b3331.tar.xz | |
dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regs
ICH_APxR1, ICH_APxR2, ICH_APxR3 are implemented only if supporting more
than 6 bits of priority. Since this is not the case, they are currently
unimplemented.
According to spec, unimplemented registers are RAZ/WI.
Change-Id: Ifd7f7a3d42b4575c2f7aff3b95d5a47ac1e61842
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20619
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/dev/isa_fake.hh')
0 files changed, 0 insertions, 0 deletions