summaryrefslogtreecommitdiff
path: root/src/dev/mips/Malta.py
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2009-07-21 01:09:05 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-21 01:09:05 -0700
commit74584d79b66b3459c72db6c74bfa9e22ee1ae23b (patch)
treef8a98156083103e9f883235e2fd91cccba76f179 /src/dev/mips/Malta.py
parent7548082d3baf578fe984c79f414dbefd96091359 (diff)
downloadgem5-74584d79b66b3459c72db6c74bfa9e22ee1ae23b.tar.xz
MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
Diffstat (limited to 'src/dev/mips/Malta.py')
-rwxr-xr-xsrc/dev/mips/Malta.py6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index d215bf329..740aa4a7f 100755
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -42,10 +42,12 @@ class MaltaCChip(BasicPioDevice):
class MaltaIO(BasicPioDevice):
type = 'MaltaIO'
- time = Param.UInt64(1136073600,
+ time = Param.Time('01/01/2009',
"System time to use (0 for actual time, default is 1/1/06)")
+ year_is_bcd = Param.Bool(False,
+ "The RTC should interpret the year as a BCD value")
malta = Param.Malta(Parent.any, "Malta")
- frequency = Param.Frequency('1050Hz', "frequency of interrupts")
+ frequency = Param.Frequency('1024Hz', "frequency of interrupts")
class MaltaPChip(BasicPioDevice):
type = 'MaltaPChip'