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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
| commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
| tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/dev/mips/SConscript | |
| parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
| parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
| download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz | |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/dev/mips/SConscript')
| -rwxr-xr-x | src/dev/mips/SConscript | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/dev/mips/SConscript b/src/dev/mips/SConscript index 22e91ff09..e83e47ebd 100755 --- a/src/dev/mips/SConscript +++ b/src/dev/mips/SConscript @@ -32,13 +32,13 @@ Import('*') if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'mips': - SimObject('MipsConsole.py') + SimObject('MipsBackdoor.py') SimObject('Malta.py') TraceFlag('Malta') TraceFlag('MC146818') - Source('console.cc') + Source('backdoor.cc') Source('malta.cc') Source('malta_cchip.cc') Source('malta_io.cc') |