dev: Explicitly specify the endianness for packet accessors.

Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.

For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.

Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 46 insertions, 46 deletions

diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 88528c4b7..2d55603f1 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -194,27 +194,27 @@ IGbE::read(PacketPtr pkt)
 
     switch (daddr) {
       case REG_CTRL:
-        pkt->set<uint32_t>(regs.ctrl());
+        pkt->setLE<uint32_t>(regs.ctrl());
         break;
       case REG_STATUS:
-        pkt->set<uint32_t>(regs.sts());
+        pkt->setLE<uint32_t>(regs.sts());
         break;
       case REG_EECD:
-        pkt->set<uint32_t>(regs.eecd());
+        pkt->setLE<uint32_t>(regs.eecd());
         break;
       case REG_EERD:
-        pkt->set<uint32_t>(regs.eerd());
+        pkt->setLE<uint32_t>(regs.eerd());
         break;
       case REG_CTRL_EXT:
-        pkt->set<uint32_t>(regs.ctrl_ext());
+        pkt->setLE<uint32_t>(regs.ctrl_ext());
         break;
       case REG_MDIC:
-        pkt->set<uint32_t>(regs.mdic());
+        pkt->setLE<uint32_t>(regs.mdic());
         break;
       case REG_ICR:
         DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
                 regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
-        pkt->set<uint32_t>(regs.icr());
+        pkt->setLE<uint32_t>(regs.icr());
         if (regs.icr.int_assert() || regs.imr == 0) {
             regs.icr = regs.icr() & ~mask(30);
             DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr());
@@ -226,55 +226,55 @@ IGbE::read(PacketPtr pkt)
       case REG_EICR:
         // This is only useful for MSI, but the driver reads it every time
         // Just don't do anything
-        pkt->set<uint32_t>(0);
+        pkt->setLE<uint32_t>(0);
         break;
       case REG_ITR:
-        pkt->set<uint32_t>(regs.itr());
+        pkt->setLE<uint32_t>(regs.itr());
         break;
       case REG_RCTL:
-        pkt->set<uint32_t>(regs.rctl());
+        pkt->setLE<uint32_t>(regs.rctl());
         break;
       case REG_FCTTV:
-        pkt->set<uint32_t>(regs.fcttv());
+        pkt->setLE<uint32_t>(regs.fcttv());
         break;
       case REG_TCTL:
-        pkt->set<uint32_t>(regs.tctl());
+        pkt->setLE<uint32_t>(regs.tctl());
         break;
       case REG_PBA:
-        pkt->set<uint32_t>(regs.pba());
+        pkt->setLE<uint32_t>(regs.pba());
         break;
       case REG_WUC:
       case REG_WUFC:
       case REG_WUS:
       case REG_LEDCTL:
-        pkt->set<uint32_t>(0); // We don't care, so just return 0
+        pkt->setLE<uint32_t>(0); // We don't care, so just return 0
         break;
       case REG_FCRTL:
-        pkt->set<uint32_t>(regs.fcrtl());
+        pkt->setLE<uint32_t>(regs.fcrtl());
         break;
       case REG_FCRTH:
-        pkt->set<uint32_t>(regs.fcrth());
+        pkt->setLE<uint32_t>(regs.fcrth());
         break;
       case REG_RDBAL:
-        pkt->set<uint32_t>(regs.rdba.rdbal());
+        pkt->setLE<uint32_t>(regs.rdba.rdbal());
         break;
       case REG_RDBAH:
-        pkt->set<uint32_t>(regs.rdba.rdbah());
+        pkt->setLE<uint32_t>(regs.rdba.rdbah());
         break;
       case REG_RDLEN:
-        pkt->set<uint32_t>(regs.rdlen());
+        pkt->setLE<uint32_t>(regs.rdlen());
         break;
       case REG_SRRCTL:
-        pkt->set<uint32_t>(regs.srrctl());
+        pkt->setLE<uint32_t>(regs.srrctl());
         break;
       case REG_RDH:
-        pkt->set<uint32_t>(regs.rdh());
+        pkt->setLE<uint32_t>(regs.rdh());
         break;
       case REG_RDT:
-        pkt->set<uint32_t>(regs.rdt());
+        pkt->setLE<uint32_t>(regs.rdt());
         break;
       case REG_RDTR:
-        pkt->set<uint32_t>(regs.rdtr());
+        pkt->setLE<uint32_t>(regs.rdtr());
         if (regs.rdtr.fpd()) {
             rxDescCache.writeback(0);
             DPRINTF(EthernetIntr,
@@ -284,65 +284,65 @@ IGbE::read(PacketPtr pkt)
         }
         break;
       case REG_RXDCTL:
-        pkt->set<uint32_t>(regs.rxdctl());
+        pkt->setLE<uint32_t>(regs.rxdctl());
         break;
       case REG_RADV:
-        pkt->set<uint32_t>(regs.radv());
+        pkt->setLE<uint32_t>(regs.radv());
         break;
       case REG_TDBAL:
-        pkt->set<uint32_t>(regs.tdba.tdbal());
+        pkt->setLE<uint32_t>(regs.tdba.tdbal());
         break;
       case REG_TDBAH:
-        pkt->set<uint32_t>(regs.tdba.tdbah());
+        pkt->setLE<uint32_t>(regs.tdba.tdbah());
         break;
       case REG_TDLEN:
-        pkt->set<uint32_t>(regs.tdlen());
+        pkt->setLE<uint32_t>(regs.tdlen());
         break;
       case REG_TDH:
-        pkt->set<uint32_t>(regs.tdh());
+        pkt->setLE<uint32_t>(regs.tdh());
         break;
       case REG_TXDCA_CTL:
-        pkt->set<uint32_t>(regs.txdca_ctl());
+        pkt->setLE<uint32_t>(regs.txdca_ctl());
         break;
       case REG_TDT:
-        pkt->set<uint32_t>(regs.tdt());
+        pkt->setLE<uint32_t>(regs.tdt());
         break;
       case REG_TIDV:
-        pkt->set<uint32_t>(regs.tidv());
+        pkt->setLE<uint32_t>(regs.tidv());
         break;
       case REG_TXDCTL:
-        pkt->set<uint32_t>(regs.txdctl());
+        pkt->setLE<uint32_t>(regs.txdctl());
         break;
       case REG_TADV:
-        pkt->set<uint32_t>(regs.tadv());
+        pkt->setLE<uint32_t>(regs.tadv());
         break;
       case REG_TDWBAL:
-        pkt->set<uint32_t>(regs.tdwba & mask(32));
+        pkt->setLE<uint32_t>(regs.tdwba & mask(32));
         break;
       case REG_TDWBAH:
-        pkt->set<uint32_t>(regs.tdwba >> 32);
+        pkt->setLE<uint32_t>(regs.tdwba >> 32);
         break;
       case REG_RXCSUM:
-        pkt->set<uint32_t>(regs.rxcsum());
+        pkt->setLE<uint32_t>(regs.rxcsum());
         break;
       case REG_RLPML:
-        pkt->set<uint32_t>(regs.rlpml);
+        pkt->setLE<uint32_t>(regs.rlpml);
         break;
       case REG_RFCTL:
-        pkt->set<uint32_t>(regs.rfctl());
+        pkt->setLE<uint32_t>(regs.rfctl());
         break;
       case REG_MANC:
-        pkt->set<uint32_t>(regs.manc());
+        pkt->setLE<uint32_t>(regs.manc());
         break;
       case REG_SWSM:
-        pkt->set<uint32_t>(regs.swsm());
+        pkt->setLE<uint32_t>(regs.swsm());
         regs.swsm.smbi(1);
         break;
       case REG_FWSM:
-        pkt->set<uint32_t>(regs.fwsm());
+        pkt->setLE<uint32_t>(regs.fwsm());
         break;
       case REG_SWFWSYNC:
-        pkt->set<uint32_t>(regs.sw_fw_sync);
+        pkt->setLE<uint32_t>(regs.sw_fw_sync);
         break;
       default:
         if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) &&
@@ -351,7 +351,7 @@ IGbE::read(PacketPtr pkt)
             !IN_RANGE(daddr, REG_CRCERRS, STATS_REGS_SIZE))
             panic("Read request to unknown register number: %#x\n", daddr);
         else
-            pkt->set<uint32_t>(0);
+            pkt->setLE<uint32_t>(0);
     };
 
     pkt->makeAtomicResponse();
@@ -375,12 +375,12 @@ IGbE::write(PacketPtr pkt)
     assert(pkt->getSize() == sizeof(uint32_t));
 
     DPRINTF(Ethernet, "Wrote device register %#X value %#X\n",
-            daddr, pkt->get<uint32_t>());
+            daddr, pkt->getLE<uint32_t>());
 
     //
     // Handle write of register here
     //
-    uint32_t val = pkt->get<uint32_t>();
+    uint32_t val = pkt->getLE<uint32_t>();
 
     Regs::RCTL oldrctl;
     Regs::TCTL oldtctl;