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authorGabe Black <gabeblack@google.com>2018-10-12 05:06:26 -0700
committerGabe Black <gabeblack@google.com>2018-10-17 20:17:44 +0000
commit2bcb2b031d4419e87337b25936a09228955dc715 (patch)
tree1da2953b4764a66bca23dfcf1656f4af205206d5 /src/dev/net/ns_gige.cc
parent2701fcb2ffe76e2cb087807e87a9114d0009b7db (diff)
downloadgem5-2bcb2b031d4419e87337b25936a09228955dc715.tar.xz
dev: Explicitly specify the endianness for packet accessors.
Generally speaking, the endianness of the data devices provide or accept is dependent on the device and not the ISA the system executes. This change makes the devices in dev pick an endianness rather than using the guest's. For the ISA bus and the UART, accesses are byte sized and so endianness doesn't matter. The ISA and PCI busses and the devices which use them are defined to be little endian. Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f Reviewed-on: https://gem5-review.googlesource.com/c/13462 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/net/ns_gige.cc')
-rw-r--r--src/dev/net/ns_gige.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/dev/net/ns_gige.cc b/src/dev/net/ns_gige.cc
index e1289b4b1..1a5adb275 100644
--- a/src/dev/net/ns_gige.cc
+++ b/src/dev/net/ns_gige.cc
@@ -209,7 +209,7 @@ NSGigE::read(PacketPtr pkt)
// don't implement all the MIB's. hopefully the kernel
// doesn't actually DEPEND upon their values
// MIB are just hardware stats keepers
- pkt->set<uint32_t>(0);
+ pkt->setLE<uint32_t>(0);
pkt->makeAtomicResponse();
return pioDelay;
} else if (daddr > 0x3FC)
@@ -427,7 +427,7 @@ NSGigE::write(PacketPtr pkt)
panic("Something is messed up!\n");
if (pkt->getSize() == sizeof(uint32_t)) {
- uint32_t reg = pkt->get<uint32_t>();
+ uint32_t reg = pkt->getLE<uint32_t>();
uint16_t rfaddr;
DPRINTF(EthernetPIO, "write data=%d data=%#x\n", reg, reg);