dev: Explicitly specify the endianness for packet accessors.

Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.

For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.

Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 13 insertions, 11 deletions

diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc
index 50341a4d3..ce9fbb6a3 100644
--- a/src/dev/net/sinic.cc
+++ b/src/dev/net/sinic.cc
@@ -248,13 +248,13 @@ Device::read(PacketPtr pkt)
     uint64_t value M5_VAR_USED = 0;
     if (pkt->getSize() == 4) {
         uint32_t reg = regData32(raddr);
-        pkt->set(reg);
+        pkt->setLE(reg);
         value = reg;
     }
 
     if (pkt->getSize() == 8) {
         uint64_t reg = regData64(raddr);
-        pkt->set(reg);
+        pkt->setLE(reg);
         value = reg;
     }
 
@@ -333,26 +333,28 @@ Device::write(PacketPtr pkt)
 
     DPRINTF(EthernetPIO,
             "write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n",
-            info.name, index, cpu, info.size == 4 ? pkt->get<uint32_t>() :
-            pkt->get<uint64_t>(), daddr, pkt->getAddr(), pkt->getSize());
+            info.name, index, cpu, info.size == 4 ?
+            pkt->getLE<uint32_t>() : pkt->getLE<uint64_t>(),
+            daddr, pkt->getAddr(), pkt->getSize());
 
     prepareWrite(cpu, index);
 
     switch (raddr) {
       case Regs::Config:
-        changeConfig(pkt->get<uint32_t>());
+        changeConfig(pkt->getLE<uint32_t>());
         break;
 
       case Regs::Command:
-        command(pkt->get<uint32_t>());
+        command(pkt->getLE<uint32_t>());
         break;
 
       case Regs::IntrStatus:
-        devIntrClear(regs.IntrStatus & pkt->get<uint32_t>());
+        devIntrClear(regs.IntrStatus &
+                pkt->getLE<uint32_t>());
         break;
 
       case Regs::IntrMask:
-        devIntrChangeMask(pkt->get<uint32_t>());
+        devIntrChangeMask(pkt->getLE<uint32_t>());
         break;
 
       case Regs::RxData:
@@ -362,10 +364,10 @@ Device::write(PacketPtr pkt)
 
         vnic.rxUnique = rxUnique++;
         vnic.RxDone = Regs::RxDone_Busy;
-        vnic.RxData = pkt->get<uint64_t>();
+        vnic.RxData = pkt->getLE<uint64_t>();
         rxBusyCount++;
 
-        if (Regs::get_RxData_Vaddr(pkt->get<uint64_t>())) {
+        if (Regs::get_RxData_Vaddr(pkt->getLE<uint64_t>())) {
             panic("vtophys not implemented in newmem");
 #ifdef SINIC_VTOPHYS
             Addr vaddr = Regs::get_RxData_Addr(reg64);
@@ -403,7 +405,7 @@ Device::write(PacketPtr pkt)
         vnic.txUnique = txUnique++;
         vnic.TxDone = Regs::TxDone_Busy;
 
-        if (Regs::get_TxData_Vaddr(pkt->get<uint64_t>())) {
+        if (Regs::get_TxData_Vaddr(pkt->getLE<uint64_t>())) {
             panic("vtophys won't work here in newmem.\n");
 #ifdef SINIC_VTOPHYS
             Addr vaddr = Regs::get_TxData_Addr(reg64);