Devices: Make EtherInts connect in the same way memory ports currently do.

--HG--
extra : convert_revision : 765b096785a77df9adc4791c9101b90696bd7be2

1 files changed, 14 insertions, 16 deletions

diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index 28e1100ae..0788b89a9 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -44,7 +44,6 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/NSGigE.hh"
-#include "params/NSGigEInt.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"
 #include "sim/stats.hh"
@@ -90,7 +89,7 @@ using namespace TheISA;
 // NSGigE PCI Device
 //
 NSGigE::NSGigE(Params *p)
-    : PciDev(p), ioEnable(false),
+    : EtherDevice(p), ioEnable(false),
       txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
       txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
       txXferLen(0), rxXferLen(0), rxDmaFree(false), txDmaFree(false),
@@ -118,6 +117,8 @@ NSGigE::NSGigE(Params *p)
 {
 
 
+    interface = new NSGigEInt(name() + ".int0", this);
+
     regsReset();
     memcpy(&rom.perfectMatch, p->hardware_address.bytes(), ETH_ADDR_LEN);
 
@@ -492,6 +493,17 @@ NSGigE::writeConfig(PacketPtr pkt)
     return configDelay;
 }
 
+EtherInt*
+NSGigE::getEthPort(const std::string &if_name, int idx)
+{
+    if (if_name == "interface") {
+       if (interface->getPeer())
+           panic("interface already connected to\n");
+       return interface;
+    }
+    return NULL;
+}
+
 /**
  * This reads the device registers, which are detailed in the NS83820
  * spec sheet
@@ -2774,20 +2786,6 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
     }
 }
 
-NSGigEInt *
-NSGigEIntParams::create()
-{
-    NSGigEInt *dev_int = new NSGigEInt(name, device);
-
-    EtherInt *p = (EtherInt *)peer;
-    if (p) {
-        dev_int->setPeer(p);
-        p->setPeer(dev_int);
-    }
-
-    return dev_int;
-}
-
 NSGigE *
 NSGigEParams::create()
 {