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| author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-11-02 11:32:01 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-11-02 11:32:01 -0500 |
| commit | b81a977e6ab7dbfd122cb778cfe3d40ca7451198 (patch) | |
| tree | 09804c27367de8cf93623ec4644bf47abf316bf9 /src/dev/ns_gige.cc | |
| parent | eb703a4b4e167e4d45f92203a1e0849f19cdba6d (diff) | |
| download | gem5-b81a977e6ab7dbfd122cb778cfe3d40ca7451198.tar.xz | |
sim: Move the draining interface into a separate base class
This patch moves the draining interface from SimObject to a separate
class that can be used by any object needing draining. However,
objects not visible to the Python code (i.e., objects not deriving
from SimObject) still depend on their parents informing them when to
drain. This patch also gets rid of the CountedDrainEvent (which isn't
really an event) and replaces it with a DrainManager.
Diffstat (limited to 'src/dev/ns_gige.cc')
| -rw-r--r-- | src/dev/ns_gige.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 0af9fbfc5..90eb14acd 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -1069,7 +1069,7 @@ NSGigE::doRxDmaRead() assert(rxDmaState == dmaIdle || rxDmaState == dmaReadWaiting); rxDmaState = dmaReading; - if (dmaPending() || getState() != Running) + if (dmaPending() || getDrainState() != Drainable::Running) rxDmaState = dmaReadWaiting; else dmaRead(rxDmaAddr, rxDmaLen, &rxDmaReadEvent, (uint8_t*)rxDmaData); @@ -1100,7 +1100,7 @@ NSGigE::doRxDmaWrite() assert(rxDmaState == dmaIdle || rxDmaState == dmaWriteWaiting); rxDmaState = dmaWriting; - if (dmaPending() || getState() != Running) + if (dmaPending() || getDrainState() != Running) rxDmaState = dmaWriteWaiting; else dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaWriteEvent, (uint8_t*)rxDmaData); @@ -1518,7 +1518,7 @@ NSGigE::doTxDmaRead() assert(txDmaState == dmaIdle || txDmaState == dmaReadWaiting); txDmaState = dmaReading; - if (dmaPending() || getState() != Running) + if (dmaPending() || getDrainState() != Running) txDmaState = dmaReadWaiting; else dmaRead(txDmaAddr, txDmaLen, &txDmaReadEvent, (uint8_t*)txDmaData); @@ -1549,7 +1549,7 @@ NSGigE::doTxDmaWrite() assert(txDmaState == dmaIdle || txDmaState == dmaWriteWaiting); txDmaState = dmaWriting; - if (dmaPending() || getState() != Running) + if (dmaPending() || getDrainState() != Running) txDmaState = dmaWriteWaiting; else dmaWrite(txDmaAddr, txDmaLen, &txDmaWriteEvent, (uint8_t*)txDmaData); @@ -2112,9 +2112,9 @@ NSGigE::recvPacket(EthPacketPtr packet) void -NSGigE::resume() +NSGigE::drainResume() { - SimObject::resume(); + Drainable::drainResume(); // During drain we could have left the state machines in a waiting state and // they wouldn't get out until some other event occured to kick them. |