summaryrefslogtreecommitdiff
path: root/src/dev/pci/CopyEngine.py
diff options
context:
space:
mode:
authorAndreas Sandberg <andreas.sandberg@arm.com>2015-12-10 10:35:16 +0000
committerAndreas Sandberg <andreas.sandberg@arm.com>2015-12-10 10:35:16 +0000
commit38e2860c36997858131dc47e1152bb583f68608e (patch)
treecb1f9959478b0a3dd06740a276e8e61fadcfaa50 /src/dev/pci/CopyEngine.py
parent139c97c9772be38577eaa52af5d1ef3607da4bcb (diff)
downloadgem5-38e2860c36997858131dc47e1152bb583f68608e.tar.xz
dev: Move the CopyEngine class to src/dev/pci
--HG-- rename : src/dev/CopyEngine.py => src/dev/pci/CopyEngine.py rename : src/dev/copy_engine.cc => src/dev/pci/copy_engine.cc rename : src/dev/copy_engine.hh => src/dev/pci/copy_engine.hh rename : src/dev/copy_engine_defs.hh => src/dev/pci/copy_engine_defs.hh
Diffstat (limited to 'src/dev/pci/CopyEngine.py')
-rw-r--r--src/dev/pci/CopyEngine.py59
1 files changed, 59 insertions, 0 deletions
diff --git a/src/dev/pci/CopyEngine.py b/src/dev/pci/CopyEngine.py
new file mode 100644
index 000000000..f1b9df1b9
--- /dev/null
+++ b/src/dev/pci/CopyEngine.py
@@ -0,0 +1,59 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+from PciDevice import PciDevice
+
+class CopyEngine(PciDevice):
+ type = 'CopyEngine'
+ cxx_header = "dev/pci/copy_engine.hh"
+ dma = VectorMasterPort("Copy engine DMA port")
+ VendorID = 0x8086
+ DeviceID = 0x1a38
+ Revision = 0xA2 # CM2 stepping (newest listed)
+ SubsystemID = 0
+ SubsystemVendorID = 0
+ Status = 0x0000
+ SubClassCode = 0x08
+ ClassCode = 0x80
+ ProgIF = 0x00
+ MaximumLatency = 0x00
+ MinimumGrant = 0xff
+ InterruptLine = 0x20
+ InterruptPin = 0x01
+ BAR0Size = '1kB'
+
+ ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
+ XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
+
+ latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
+ latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
+
+