dev: Rewrite PCI host functionality

The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

  * Configurable configuration space decoding. The number of bits
    dedicated to a device is a prameter, making it possible to support
    both CAM, ECAM, and legacy mappings.

  * Basic interrupt mapping using the interruptLine value from a
    device's configuration space. This behavior is the same as in the
    old implementation. More advanced controllers can override the
    interrupt mapping method to dynamically assign host interrupts to
    PCI devices.

  * Simple (base + addr) remapping from the PCI bus's address space to
    physical addresses for PIO, memory, and DMA.

1 files changed, 228 insertions, 0 deletions

diff --git a/src/dev/pci/host.cc b/src/dev/pci/host.cc
new file mode 100644
index 000000000..bcf49df86
--- /dev/null
+++ b/src/dev/pci/host.cc
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "dev/pci/host.hh"
+
+#include <utility>
+
+#include "debug/PciHost.hh"
+#include "dev/pcidev.hh"
+#include "dev/platform.hh"
+#include "params/GenericPciHost.hh"
+#include "params/PciHost.hh"
+
+
+PciHost::PciHost(const PciHostParams *p)
+    : PioDevice(p)
+{
+}
+
+PciHost::~PciHost()
+{
+}
+
+PciHost::DeviceInterface
+PciHost::registerDevice(PciDevice *device, PciBusAddr bus_addr, PciIntPin pin)
+{
+    auto map_entry = devices.emplace(bus_addr, device);
+
+    DPRINTF(PciHost, "%02x:%02x.%i: Registering device\n",
+            bus_addr.bus, bus_addr.dev, bus_addr.func);
+
+    fatal_if(!map_entry.second,
+             "%02x:%02x.%i: PCI bus ID collision\n",
+             bus_addr.bus, bus_addr.dev, bus_addr.func);
+
+    return DeviceInterface(*this, bus_addr, pin);
+}
+
+PciDevice *
+PciHost::getDevice(const PciBusAddr &addr)
+{
+    auto device = devices.find(addr);
+    return device != devices.end() ? device->second : nullptr;
+}
+
+const PciDevice *
+PciHost::getDevice(const PciBusAddr &addr) const
+{
+    auto device = devices.find(addr);
+    return device != devices.end() ? device->second : nullptr;
+}
+
+PciHost::DeviceInterface::DeviceInterface(
+    PciHost &_host,
+    PciBusAddr &bus_addr, PciIntPin interrupt_pin)
+    : host(_host),
+      busAddr(bus_addr), interruptPin(interrupt_pin)
+{
+}
+
+const std::string
+PciHost::DeviceInterface::name() const
+{
+    return csprintf("%s.interface[%02x:%02x.%i]",
+                    host.name(), busAddr.bus, busAddr.dev, busAddr.func);
+}
+
+void
+PciHost::DeviceInterface::postInt()
+{
+    DPRINTF(PciHost, "postInt\n");
+
+    host.postInt(busAddr, interruptPin);
+}
+
+void
+PciHost::DeviceInterface::clearInt()
+{
+    DPRINTF(PciHost, "clearInt\n");
+
+    host.clearInt(busAddr, interruptPin);
+}
+
+
+GenericPciHost::GenericPciHost(const GenericPciHostParams *p)
+    : PciHost(p),
+      platform(*p->platform),
+      confBase(p->conf_base), confSize(p->conf_size),
+      confDeviceBits(p->conf_device_bits),
+      pciPioBase(p->pci_pio_base), pciMemBase(p->pci_mem_base),
+      pciDmaBase(p->pci_dma_base)
+{
+}
+
+GenericPciHost::~GenericPciHost()
+{
+}
+
+
+Tick
+GenericPciHost::read(PacketPtr pkt)
+{
+    const auto dev_addr(decodeAddress(pkt->getAddr() - confBase));
+    const Addr size(pkt->getSize());
+
+    DPRINTF(PciHost, "%02x:%02x.%i: read: offset=0x%x, size=0x%x\n",
+            dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func,
+            dev_addr.second,
+            size);
+
+    PciDevice *const pci_dev(getDevice(dev_addr.first));
+    if (pci_dev) {
+        // @todo Remove this after testing
+        pkt->headerDelay = pkt->payloadDelay = 0;
+        return pci_dev->readConfig(pkt);
+    } else {
+        uint8_t *pkt_data(pkt->getPtr<uint8_t>());
+        std::fill(pkt_data, pkt_data + size, 0xFF);
+        pkt->makeAtomicResponse();
+        return 0;
+    }
+}
+
+Tick
+GenericPciHost::write(PacketPtr pkt)
+{
+    const auto dev_addr(decodeAddress(pkt->getAddr() - confBase));
+
+    DPRINTF(PciHost, "%02x:%02x.%i: write: offset=0x%x, size=0x%x\n",
+            dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func,
+            dev_addr.second,
+            pkt->getSize());
+
+    PciDevice *const pci_dev(getDevice(dev_addr.first));
+    panic_if(!pci_dev,
+             "%02x:%02x.%i: Write to config space on non-existent PCI device\n",
+             dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func);
+
+    // @todo Remove this after testing
+    pkt->headerDelay = pkt->payloadDelay = 0;
+
+    return pci_dev->writeConfig(pkt);
+}
+
+AddrRangeList
+GenericPciHost::getAddrRanges() const
+{
+    return AddrRangeList({ RangeSize(confBase, confSize) });
+}
+
+std::pair<PciBusAddr, Addr>
+GenericPciHost::decodeAddress(Addr addr)
+{
+    const Addr offset(addr & mask(confDeviceBits));
+    const Addr bus_addr(addr >> confDeviceBits);
+
+    return std::make_pair(
+        PciBusAddr(bits(bus_addr, 15, 8),
+                   bits(bus_addr,  7, 3),
+                   bits(bus_addr,  2, 0)),
+        offset);
+}
+
+
+void
+GenericPciHost::postInt(const PciBusAddr &addr, PciIntPin pin)
+{
+    platform.postPciInt(mapPciInterrupt(addr, pin));
+}
+
+void
+GenericPciHost::clearInt(const PciBusAddr &addr, PciIntPin pin)
+{
+    platform.clearPciInt(mapPciInterrupt(addr, pin));
+}
+
+
+uint32_t
+GenericPciHost::mapPciInterrupt(const PciBusAddr &addr, PciIntPin pin) const
+{
+    const PciDevice *dev(getDevice(addr));
+    assert(dev);
+
+    return dev->interruptLine();
+}
+
+
+GenericPciHost *
+GenericPciHostParams::create()
+{
+    return new GenericPciHost(this);
+}