dev: Explicitly specify the endianness for packet accessors.

Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.

For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.

Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2 files changed, 58 insertions, 54 deletions

diff --git a/src/dev/pci/copy_engine.cc b/src/dev/pci/copy_engine.cc
index 7c87da1c0..7f8959aca 100644
--- a/src/dev/pci/copy_engine.cc
+++ b/src/dev/pci/copy_engine.cc
@@ -193,20 +193,20 @@ CopyEngine::read(PacketPtr pkt)
         switch (daddr) {
           case GEN_CHANCOUNT:
             assert(size == sizeof(regs.chanCount));
-            pkt->set<uint8_t>(regs.chanCount);
+            pkt->setLE<uint8_t>(regs.chanCount);
             break;
           case GEN_XFERCAP:
             assert(size == sizeof(regs.xferCap));
-            pkt->set<uint8_t>(regs.xferCap);
+            pkt->setLE<uint8_t>(regs.xferCap);
             break;
           case GEN_INTRCTRL:
             assert(size == sizeof(uint8_t));
-            pkt->set<uint8_t>(regs.intrctrl());
+            pkt->setLE<uint8_t>(regs.intrctrl());
             regs.intrctrl.master_int_enable(0);
             break;
           case GEN_ATTNSTATUS:
             assert(size == sizeof(regs.attnStatus));
-            pkt->set<uint32_t>(regs.attnStatus);
+            pkt->setLE<uint32_t>(regs.attnStatus);
             regs.attnStatus = 0;
             break;
           default:
@@ -244,42 +244,42 @@ CopyEngine::CopyEngineChannel::channelRead(Packet *pkt, Addr daddr, int size)
     switch (daddr) {
       case CHAN_CONTROL:
         assert(size == sizeof(uint16_t));
-        pkt->set<uint16_t>(cr.ctrl());
+        pkt->setLE<uint16_t>(cr.ctrl());
         cr.ctrl.in_use(1);
         break;
       case CHAN_STATUS:
         assert(size == sizeof(uint64_t));
-        pkt->set<uint64_t>(cr.status() | (busy ? 0 : 1));
+        pkt->setLE<uint64_t>(cr.status() | (busy ? 0 : 1));
         break;
       case CHAN_CHAINADDR:
         assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
         if (size == sizeof(uint64_t))
-            pkt->set<uint64_t>(cr.descChainAddr);
+            pkt->setLE<uint64_t>(cr.descChainAddr);
         else
-            pkt->set<uint32_t>(bits(cr.descChainAddr,0,31));
+            pkt->setLE<uint32_t>(bits(cr.descChainAddr,0,31));
         break;
       case CHAN_CHAINADDR_HIGH:
         assert(size == sizeof(uint32_t));
-        pkt->set<uint32_t>(bits(cr.descChainAddr,32,63));
+        pkt->setLE<uint32_t>(bits(cr.descChainAddr,32,63));
         break;
       case CHAN_COMMAND:
         assert(size == sizeof(uint8_t));
-        pkt->set<uint32_t>(cr.command());
+        pkt->setLE<uint32_t>(cr.command());
         break;
       case CHAN_CMPLNADDR:
         assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
         if (size == sizeof(uint64_t))
-            pkt->set<uint64_t>(cr.completionAddr);
+            pkt->setLE<uint64_t>(cr.completionAddr);
         else
-            pkt->set<uint32_t>(bits(cr.completionAddr,0,31));
+            pkt->setLE<uint32_t>(bits(cr.completionAddr,0,31));
         break;
       case CHAN_CMPLNADDR_HIGH:
         assert(size == sizeof(uint32_t));
-        pkt->set<uint32_t>(bits(cr.completionAddr,32,63));
+        pkt->setLE<uint32_t>(bits(cr.completionAddr,32,63));
         break;
       case CHAN_ERROR:
         assert(size == sizeof(uint32_t));
-        pkt->set<uint32_t>(cr.error());
+        pkt->setLE<uint32_t>(cr.error());
         break;
       default:
         panic("Read request to unknown channel register number: (%d)%#x\n",
@@ -308,17 +308,21 @@ CopyEngine::write(PacketPtr pkt)
     ///
 
     if (size == sizeof(uint64_t)) {
-        uint64_t val M5_VAR_USED = pkt->get<uint64_t>();
-        DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
+        uint64_t val M5_VAR_USED = pkt->getLE<uint64_t>();
+        DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
+                daddr, val);
     } else if (size == sizeof(uint32_t)) {
-        uint32_t val M5_VAR_USED = pkt->get<uint32_t>();
-        DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
+        uint32_t val M5_VAR_USED = pkt->getLE<uint32_t>();
+        DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
+                daddr, val);
     } else if (size == sizeof(uint16_t)) {
-        uint16_t val M5_VAR_USED = pkt->get<uint16_t>();
-        DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
+        uint16_t val M5_VAR_USED = pkt->getLE<uint16_t>();
+        DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
+                daddr, val);
     } else if (size == sizeof(uint8_t)) {
-        uint8_t val M5_VAR_USED = pkt->get<uint8_t>();
-        DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
+        uint8_t val M5_VAR_USED = pkt->getLE<uint8_t>();
+        DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
+                daddr, val);
     } else {
         panic("Unknown size for MMIO access: %d\n", size);
     }
@@ -332,7 +336,7 @@ CopyEngine::write(PacketPtr pkt)
                     daddr);
             break;
           case GEN_INTRCTRL:
-            regs.intrctrl.master_int_enable(bits(pkt->get<uint8_t>(),0,1));
+            regs.intrctrl.master_int_enable(bits(pkt->getLE<uint8_t>(), 0, 1));
             break;
           default:
             panic("Read request to unknown register number: %#x\n", daddr);
@@ -370,7 +374,7 @@ CopyEngine::CopyEngineChannel::channelWrite(Packet *pkt, Addr daddr, int size)
         assert(size == sizeof(uint16_t));
         int old_int_disable;
         old_int_disable = cr.ctrl.interrupt_disable();
-        cr.ctrl(pkt->get<uint16_t>());
+        cr.ctrl(pkt->getLE<uint16_t>());
         if (cr.ctrl.interrupt_disable())
             cr.ctrl.interrupt_disable(0);
         else
@@ -384,39 +388,39 @@ CopyEngine::CopyEngineChannel::channelWrite(Packet *pkt, Addr daddr, int size)
       case CHAN_CHAINADDR:
         assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
         if (size == sizeof(uint64_t))
-            cr.descChainAddr = pkt->get<uint64_t>();
+            cr.descChainAddr = pkt->getLE<uint64_t>();
         else
-            cr.descChainAddr =  (uint64_t)pkt->get<uint32_t>() |
+            cr.descChainAddr =  (uint64_t)pkt->getLE<uint32_t>() |
                 (cr.descChainAddr & ~mask(32));
         DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
         break;
       case CHAN_CHAINADDR_HIGH:
         assert(size == sizeof(uint32_t));
-        cr.descChainAddr =  ((uint64_t)pkt->get<uint32_t>() <<32) |
+        cr.descChainAddr =  ((uint64_t)pkt->getLE<uint32_t>() << 32) |
             (cr.descChainAddr & mask(32));
         DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
         break;
       case CHAN_COMMAND:
         assert(size == sizeof(uint8_t));
-        cr.command(pkt->get<uint8_t>());
+        cr.command(pkt->getLE<uint8_t>());
         recvCommand();
         break;
       case CHAN_CMPLNADDR:
         assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
         if (size == sizeof(uint64_t))
-            cr.completionAddr = pkt->get<uint64_t>();
+            cr.completionAddr = pkt->getLE<uint64_t>();
         else
-            cr.completionAddr =  pkt->get<uint32_t>() |
+            cr.completionAddr =  pkt->getLE<uint32_t>() |
                 (cr.completionAddr & ~mask(32));
         break;
       case CHAN_CMPLNADDR_HIGH:
         assert(size == sizeof(uint32_t));
-        cr.completionAddr =  ((uint64_t)pkt->get<uint32_t>() <<32) |
+        cr.completionAddr =  ((uint64_t)pkt->getLE<uint32_t>() <<32) |
             (cr.completionAddr & mask(32));
         break;
       case CHAN_ERROR:
         assert(size == sizeof(uint32_t));
-        cr.error(~pkt->get<uint32_t>() & cr.error());
+        cr.error(~pkt->getLE<uint32_t>() & cr.error());
         break;
       default:
         panic("Read request to unknown channel register number: (%d)%#x\n",
diff --git a/src/dev/pci/device.cc b/src/dev/pci/device.cc
index 4d9d29b1d..1097573f8 100644
--- a/src/dev/pci/device.cc
+++ b/src/dev/pci/device.cc
@@ -228,13 +228,13 @@ PciDevice::readConfig(PacketPtr pkt)
                   "not implemented for %s!\n", this->name());
         switch (pkt->getSize()) {
             case sizeof(uint8_t):
-                pkt->set<uint8_t>(0);
+                pkt->setLE<uint8_t>(0);
                 break;
             case sizeof(uint16_t):
-                pkt->set<uint16_t>(0);
+                pkt->setLE<uint16_t>(0);
                 break;
             case sizeof(uint32_t):
-                pkt->set<uint32_t>(0);
+                pkt->setLE<uint32_t>(0);
                 break;
             default:
                 panic("invalid access size(?) for PCI configspace!\n");
@@ -245,25 +245,25 @@ PciDevice::readConfig(PacketPtr pkt)
 
     switch (pkt->getSize()) {
       case sizeof(uint8_t):
-        pkt->set<uint8_t>(config.data[offset]);
+        pkt->setLE<uint8_t>(config.data[offset]);
         DPRINTF(PciDevice,
             "readConfig:  dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
             _busAddr.dev, _busAddr.func, offset,
-            (uint32_t)pkt->get<uint8_t>());
+            (uint32_t)pkt->getLE<uint8_t>());
         break;
       case sizeof(uint16_t):
-        pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
+        pkt->setLE<uint16_t>(*(uint16_t*)&config.data[offset]);
         DPRINTF(PciDevice,
             "readConfig:  dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
             _busAddr.dev, _busAddr.func, offset,
-            (uint32_t)pkt->get<uint16_t>());
+            (uint32_t)pkt->getLE<uint16_t>());
         break;
       case sizeof(uint32_t):
-        pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
+        pkt->setLE<uint32_t>(*(uint32_t*)&config.data[offset]);
         DPRINTF(PciDevice,
             "readConfig:  dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
             _busAddr.dev, _busAddr.func, offset,
-            (uint32_t)pkt->get<uint32_t>());
+            (uint32_t)pkt->getLE<uint32_t>());
         break;
       default:
         panic("invalid access size(?) for PCI configspace!\n");
@@ -310,13 +310,13 @@ PciDevice::writeConfig(PacketPtr pkt)
       case sizeof(uint8_t):
         switch (offset) {
           case PCI0_INTERRUPT_LINE:
-            config.interruptLine = pkt->get<uint8_t>();
+            config.interruptLine = pkt->getLE<uint8_t>();
             break;
           case PCI_CACHE_LINE_SIZE:
-            config.cacheLineSize = pkt->get<uint8_t>();
+            config.cacheLineSize = pkt->getLE<uint8_t>();
             break;
           case PCI_LATENCY_TIMER:
-            config.latencyTimer = pkt->get<uint8_t>();
+            config.latencyTimer = pkt->getLE<uint8_t>();
             break;
           /* Do nothing for these read-only registers */
           case PCI0_INTERRUPT_PIN:
@@ -331,18 +331,18 @@ PciDevice::writeConfig(PacketPtr pkt)
         DPRINTF(PciDevice,
             "writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
             _busAddr.dev, _busAddr.func, offset,
-            (uint32_t)pkt->get<uint8_t>());
+            (uint32_t)pkt->getLE<uint8_t>());
         break;
       case sizeof(uint16_t):
         switch (offset) {
           case PCI_COMMAND:
-            config.command = pkt->get<uint8_t>();
+            config.command = pkt->getLE<uint8_t>();
             break;
           case PCI_STATUS:
-            config.status = pkt->get<uint8_t>();
+            config.status = pkt->getLE<uint8_t>();
             break;
           case PCI_CACHE_LINE_SIZE:
-            config.cacheLineSize = pkt->get<uint8_t>();
+            config.cacheLineSize = pkt->getLE<uint8_t>();
             break;
           default:
             panic("writing to a read only register");
@@ -350,7 +350,7 @@ PciDevice::writeConfig(PacketPtr pkt)
         DPRINTF(PciDevice,
             "writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
             _busAddr.dev, _busAddr.func, offset,
-            (uint32_t)pkt->get<uint16_t>());
+            (uint32_t)pkt->getLE<uint16_t>());
         break;
       case sizeof(uint32_t):
         switch (offset) {
@@ -366,7 +366,7 @@ PciDevice::writeConfig(PacketPtr pkt)
                 if (!legacyIO[barnum]) {
                     // convert BAR values to host endianness
                     uint32_t he_old_bar = letoh(config.baseAddr[barnum]);
-                    uint32_t he_new_bar = letoh(pkt->get<uint32_t>());
+                    uint32_t he_new_bar = letoh(pkt->getLE<uint32_t>());
 
                     uint32_t bar_mask =
                         BAR_IO_SPACE(he_old_bar) ? BAR_IO_MASK : BAR_MEM_MASK;
@@ -393,17 +393,17 @@ PciDevice::writeConfig(PacketPtr pkt)
             break;
 
           case PCI0_ROM_BASE_ADDR:
-            if (letoh(pkt->get<uint32_t>()) == 0xfffffffe)
+            if (letoh(pkt->getLE<uint32_t>()) == 0xfffffffe)
                 config.expansionROM = htole((uint32_t)0xffffffff);
             else
-                config.expansionROM = pkt->get<uint32_t>();
+                config.expansionROM = pkt->getLE<uint32_t>();
             break;
 
           case PCI_COMMAND:
             // This could also clear some of the error bits in the Status
             // register. However they should never get set, so lets ignore
             // it for now
-            config.command = pkt->get<uint32_t>();
+            config.command = pkt->getLE<uint32_t>();
             break;
 
           default:
@@ -412,7 +412,7 @@ PciDevice::writeConfig(PacketPtr pkt)
         DPRINTF(PciDevice,
             "writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
             _busAddr.dev, _busAddr.func, offset,
-            (uint32_t)pkt->get<uint32_t>());
+            (uint32_t)pkt->getLE<uint32_t>());
         break;
       default:
         panic("invalid access size(?) for PCI configspace!\n");