diff options
| author | Steve Reinhardt <stever@gmail.com> | 2008-03-25 10:04:52 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2008-03-25 10:04:52 -0400 |
| commit | ba1f7d31e0f28d64df2fb03fe4b69182b9d3ff34 (patch) | |
| tree | 33f52cbce6ac4fa332976d2a53977c7bde876c6b /src/dev/rtcreg.h | |
| parent | 29be31ce3139c36f596e6edafbd3d253ee2200b3 (diff) | |
| parent | 93dd1978a7750ba7cce04ae4401f5c6689290038 (diff) | |
| download | gem5-ba1f7d31e0f28d64df2fb03fe4b69182b9d3ff34.tar.xz | |
Automated merge with ssh://daystrom.m5sim.org//repo/m5
--HG--
extra : convert_revision : 7922848bb1145bcb2ee07d672d21cfe2dd98fc03
Diffstat (limited to 'src/dev/rtcreg.h')
| -rw-r--r-- | src/dev/rtcreg.h | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/src/dev/rtcreg.h b/src/dev/rtcreg.h index 37255777b..b1406c464 100644 --- a/src/dev/rtcreg.h +++ b/src/dev/rtcreg.h @@ -30,32 +30,32 @@ * Nathan Binkert */ -#define RTC_SEC 0x00 -#define RTC_SEC_ALRM 0x01 -#define RTC_MIN 0x02 -#define RTC_MIN_ALRM 0x03 -#define RTC_HR 0x04 -#define RTC_HR_ALRM 0x05 -#define RTC_DOW 0x06 -#define RTC_DOM 0x07 -#define RTC_MON 0x08 -#define RTC_YEAR 0x09 +static const int RTC_SEC = 0x00; +static const int RTC_SEC_ALRM = 0x01; +static const int RTC_MIN = 0x02; +static const int RTC_MIN_ALRM = 0x03; +static const int RTC_HR = 0x04; +static const int RTC_HR_ALRM = 0x05; +static const int RTC_DOW = 0x06; +static const int RTC_DOM = 0x07; +static const int RTC_MON = 0x08; +static const int RTC_YEAR = 0x09; -#define RTC_STAT_REGA 0x0A -#define RTCA_1024HZ 0x06 /* 1024Hz periodic interrupt frequency */ -#define RTCA_32768HZ 0x20 /* 22-stage divider, 32.768KHz timebase */ -#define RTCA_UIP 0x80 /* 1 = date and time update in progress */ +static const int RTC_STAT_REGA = 0x0A; +static const int RTCA_1024HZ = 0x06; /* 1024Hz periodic interrupt frequency */ +static const int RTCA_32768HZ = 0x20; /* 22-stage divider, 32.768KHz timebase */ +static const int RTCA_UIP = 0x80; /* 1 = date and time update in progress */ -#define RTC_STAT_REGB 0x0B -#define RTCB_DST 0x01 /* USA Daylight Savings Time enable */ -#define RTCB_24HR 0x02 /* 0 = 12 hours, 1 = 24 hours */ -#define RTCB_BIN 0x04 /* 0 = BCD, 1 = Binary coded time */ -#define RTCB_SQWE 0x08 /* 1 = output sqare wave at SQW pin */ -#define RTCB_UPDT_IE 0x10 /* 1 = enable update-ended interrupt */ -#define RTCB_ALRM_IE 0x20 /* 1 = enable alarm interrupt */ -#define RTCB_PRDC_IE 0x40 /* 1 = enable periodic clock interrupt */ -#define RTCB_NO_UPDT 0x80 /* stop clock updates */ +static const int RTC_STAT_REGB = 0x0B; +static const int RTCB_DST = 0x01; /* USA Daylight Savings Time enable */ +static const int RTCB_24HR = 0x02; /* 0 = 12 hours, 1 = 24 hours */ +static const int RTCB_BIN = 0x04; /* 0 = BCD, 1 = Binary coded time */ +static const int RTCB_SQWE = 0x08; /* 1 = output sqare wave at SQW pin */ +static const int RTCB_UPDT_IE = 0x10; /* 1 = enable update-ended interrupt */ +static const int RTCB_ALRM_IE = 0x20; /* 1 = enable alarm interrupt */ +static const int RTCB_PRDC_IE = 0x40; /* 1 = enable periodic clock interrupt */ +static const int RTCB_NO_UPDT = 0x80; /* stop clock updates */ -#define RTC_STAT_REGC 0x0C -#define RTC_STAT_REGD 0x0D +static const int RTC_STAT_REGC = 0x0C; +static const int RTC_STAT_REGD = 0x0D; |