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author | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-04-08 15:56:06 -0500 |
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committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-04-08 15:56:06 -0500 |
commit | f05cb84ed1a61f81c26e4ea22f98454d12f069aa (patch) | |
tree | 271f47eceadbf5a52597ab4c767ecf7d3ee2e0ff /src/dev/sparc/t1000.cc | |
parent | b5770ff5e06a2ef169a648c2abb72dde488dec98 (diff) | |
download | gem5-f05cb84ed1a61f81c26e4ea22f98454d12f069aa.tar.xz |
ext: Add SST connector
This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.
These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
Diffstat (limited to 'src/dev/sparc/t1000.cc')
0 files changed, 0 insertions, 0 deletions