sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.

1 files changed, 4 insertions, 0 deletions

diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index 03a59ac67..511f54b2c 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -36,22 +36,26 @@ from Uart import Uart8250
 
 class MmDisk(BasicPioDevice):
     type = 'MmDisk'
+    cxx_header = "dev/sparc/mm_disk.hh"
     image = Param.DiskImage("Disk Image")
     pio_addr = 0x1F40000000
 
 class DumbTOD(BasicPioDevice):
     type = 'DumbTOD'
+    cxx_header = "dev/sparc/dtod.hh"
     time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
     pio_addr = 0xfff0c1fff8
 
 class Iob(PioDevice):
     type = 'Iob'
+    cxx_header = "dev/sparc/iob.hh"
     platform = Param.Platform(Parent.any, "Platform this device is part of.")
     pio_latency = Param.Latency('1ns', "Programed IO latency")
 
 
 class T1000(Platform):
     type = 'T1000'
+    cxx_header = "dev/sparc/t1000.hh"
     system = Param.System(Parent.any, "system")
 
     fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)