Merge ARM into the head. ARM will compile but may not actually work.

4 files changed, 36 insertions, 12 deletions

diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index a033e27e2..cbf390737 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -29,9 +29,9 @@
 from m5.params import *
 from m5.proxy import *
 from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
-from Uart import Uart8250
 from Platform import Platform
-from SimConsole import SimConsole
+from Terminal import Terminal
+from Uart import Uart8250
 
 
 class MmDisk(BasicPioDevice):
@@ -98,11 +98,11 @@ class T1000(Platform):
     fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
             #warn_access="Accessing SSI -- Unimplemented!")
 
-    hconsole = SimConsole()
+    hterm = Terminal()
     hvuart = Uart8250(pio_addr=0xfff0c2c000)
     htod = DumbTOD()
 
-    pconsole = SimConsole()
+    pterm = Terminal()
     puart0 = Uart8250(pio_addr=0x1f10000000)
 
     iob = Iob()
@@ -116,8 +116,8 @@ class T1000(Platform):
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-        self.hvuart.sim_console = self.hconsole
-        self.puart0.sim_console = self.pconsole
+        self.hvuart.terminal = self.hterm
+        self.puart0.terminal = self.pterm
         self.fake_clk.pio = bus.port
         self.fake_membnks.pio = bus.port
         self.fake_l2_1.pio = bus.port
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index 6608fc64a..4543dd07b 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -120,7 +120,7 @@ void
 Iob::readJBus(PacketPtr pkt)
 {
         Addr accessAddr = pkt->getAddr() - iobJBusAddr;
-        int cpuid = pkt->req->getCpuNum();
+        int cpuid = pkt->req->contextId();
         int index;
         uint64_t data;
 
@@ -235,7 +235,7 @@ void
 Iob::writeJBus(PacketPtr pkt)
 {
         Addr accessAddr = pkt->getAddr() - iobJBusAddr;
-        int cpuid = pkt->req->getCpuNum();
+        int cpuid = pkt->req->contextId();
         int index;
         uint64_t data;
 
@@ -276,7 +276,7 @@ void
 Iob::generateIpi(Type type, int cpu_id, int vector)
 {
     SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset();
-    if (cpu_id >= sys->getNumCPUs())
+    if (cpu_id >= sys->numContexts())
         return;
 
     switch (type) {
diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc
index 49e44af55..88fb358ef 100644
--- a/src/dev/sparc/t1000.cc
+++ b/src/dev/sparc/t1000.cc
@@ -37,8 +37,8 @@
 #include <vector>
 
 #include "cpu/intr_control.hh"
-#include "dev/simconsole.hh"
 #include "dev/sparc/t1000.hh"
+#include "dev/terminal.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -94,7 +94,21 @@ T1000::pciToDma(Addr pciAddr) const
 
 
 Addr
-T1000::calcConfigAddr(int bus, int dev, int func)
+T1000::calcPciConfigAddr(int bus, int dev, int func)
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+Addr
+T1000::calcPciIOAddr(Addr addr)
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+Addr
+T1000::calcPciMemAddr(Addr addr)
 {
     panic("Need implementation\n");
     M5_DUMMY_RETURN
diff --git a/src/dev/sparc/t1000.hh b/src/dev/sparc/t1000.hh
index 76de0a550..01ff3d319 100644
--- a/src/dev/sparc/t1000.hh
+++ b/src/dev/sparc/t1000.hh
@@ -91,7 +91,17 @@ class T1000 : public Platform
     /**
      * Calculate the configuration address given a bus/dev/func.
      */
-    virtual Addr calcConfigAddr(int bus, int dev, int func);
+    virtual Addr calcPciConfigAddr(int bus, int dev, int func);
+
+    /**
+     * Calculate the address for an IO location on the PCI bus.
+     */
+    virtual Addr calcPciIOAddr(Addr addr);
+
+    /**
+     * Calculate the address for a memory location on the PCI bus.
+     */
+    virtual Addr calcPciMemAddr(Addr addr);
 };
 
 #endif // __DEV_T1000_HH__