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authorGabe Black <gblack@eecs.umich.edu>2006-06-12 00:49:24 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-06-12 00:49:24 -0400
commit15a8f050605919579e81b6abb98a0b596334216d (patch)
tree583b0b30f13d9874a69015d58d041ce2d7352960 /src/dev/tsunami_cchip.cc
parent60a734e1750f3c051fe92fea6f12158db6e2dcb9 (diff)
parentdf4b4f001e4db902297acf3b75480e4886e4e882 (diff)
downloadgem5-15a8f050605919579e81b6abb98a0b596334216d.tar.xz
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem src/arch/sparc/regfile.hh: Hand Merge --HG-- extra : convert_revision : c47202689202069892524a7d71962082469996ee
Diffstat (limited to 'src/dev/tsunami_cchip.cc')
-rw-r--r--src/dev/tsunami_cchip.cc21
1 files changed, 10 insertions, 11 deletions
diff --git a/src/dev/tsunami_cchip.cc b/src/dev/tsunami_cchip.cc
index 146321b9f..3feb7439f 100644
--- a/src/dev/tsunami_cchip.cc
+++ b/src/dev/tsunami_cchip.cc
@@ -24,6 +24,9 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Ron Dreslinski
*/
/** @file
@@ -40,7 +43,7 @@
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/port.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
@@ -76,7 +79,6 @@ TsunamiCChip::read(Packet *pkt)
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
- pkt->time += pioDelay;
Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
Addr daddr = (pkt->getAddr() - pioAddr);
@@ -182,9 +184,6 @@ TsunamiCChip::read(Packet *pkt)
Tick
TsunamiCChip::write(Packet *pkt)
{
- pkt->time += pioDelay;
-
-
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = pkt->getAddr() - pioAddr;
Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
@@ -369,7 +368,7 @@ TsunamiCChip::write(Packet *pkt)
void
TsunamiCChip::clearIPI(uint64_t ipintr)
{
- int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+ int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(numcpus <= Tsunami::Max_CPUs);
if (ipintr) {
@@ -395,7 +394,7 @@ TsunamiCChip::clearIPI(uint64_t ipintr)
void
TsunamiCChip::clearITI(uint64_t itintr)
{
- int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+ int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(numcpus <= Tsunami::Max_CPUs);
if (itintr) {
@@ -415,7 +414,7 @@ TsunamiCChip::clearITI(uint64_t itintr)
void
TsunamiCChip::reqIPI(uint64_t ipreq)
{
- int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+ int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(numcpus <= Tsunami::Max_CPUs);
if (ipreq) {
@@ -442,7 +441,7 @@ TsunamiCChip::reqIPI(uint64_t ipreq)
void
TsunamiCChip::postRTC()
{
- int size = tsunami->intrctrl->cpu->system->execContexts.size();
+ int size = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(size <= Tsunami::Max_CPUs);
for (int i = 0; i < size; i++) {
@@ -460,7 +459,7 @@ void
TsunamiCChip::postDRIR(uint32_t interrupt)
{
uint64_t bitvector = ULL(1) << interrupt;
- uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+ uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(size <= Tsunami::Max_CPUs);
drir |= bitvector;
@@ -478,7 +477,7 @@ void
TsunamiCChip::clearDRIR(uint32_t interrupt)
{
uint64_t bitvector = ULL(1) << interrupt;
- uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+ uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(size <= Tsunami::Max_CPUs);
if (drir & bitvector)