diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-20 11:20:17 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-08 10:32:54 +0000 |
| commit | d6c204c67d42a3cea9d603888ec52a8d8dacf1a3 (patch) | |
| tree | 3c5c0f263d122a4d13901e432ff408bfa905f1f3 /src/dev/uart8250.cc | |
| parent | 344911b885114b8401482679202aaee89fa8b29b (diff) | |
| download | gem5-d6c204c67d42a3cea9d603888ec52a8d8dacf1a3.tar.xz | |
dev: Refactor UART->Terminal interface
The UART models currently assume that they are always wired to a
terminal. While true at the moment, this isn't necessarily a valid
assumption. This change introduces the SerialDevice class that defines
the interface for serial devices. Currently, Terminal is the only
class that implements this interface.
Change-Id: I74fefafbbaf5ac1ec0d4ec0b5a0f4b246fdad305
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4289
Reviewed-by: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/dev/uart8250.cc')
| -rw-r--r-- | src/dev/uart8250.cc | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc index 482135c7b..f99b2472b 100644 --- a/src/dev/uart8250.cc +++ b/src/dev/uart8250.cc @@ -42,7 +42,6 @@ #include "config/the_isa.hh" #include "debug/Uart.hh" #include "dev/platform.hh" -#include "dev/terminal.hh" #include "mem/packet.hh" #include "mem/packet_access.hh" @@ -108,8 +107,8 @@ Uart8250::read(PacketPtr pkt) switch (daddr) { case 0x0: if (!(LCR & 0x80)) { // read byte - if (term->dataAvailable()) - pkt->set(term->in()); + if (device->dataAvailable()) + pkt->set(device->readData()); else { pkt->set((uint8_t)0); // A limited amount of these are ok. @@ -118,7 +117,7 @@ Uart8250::read(PacketPtr pkt) status &= ~RX_INT; platform->clearConsoleInt(); - if (term->dataAvailable() && (IER & UART_IER_RDI)) + if (device->dataAvailable() && (IER & UART_IER_RDI)) scheduleIntr(&rxIntrEvent); } else { // dll divisor latch ; @@ -154,7 +153,7 @@ Uart8250::read(PacketPtr pkt) uint8_t lsr; lsr = 0; // check if there are any bytes to be read - if (term->dataAvailable()) + if (device->dataAvailable()) lsr = UART_LSR_DR; lsr |= UART_LSR_TEMT | UART_LSR_THRE; pkt->set(lsr); @@ -190,7 +189,7 @@ Uart8250::write(PacketPtr pkt) switch (daddr) { case 0x0: if (!(LCR & 0x80)) { // write byte - term->out(pkt->get<uint8_t>()); + device->writeData(pkt->get<uint8_t>()); platform->clearConsoleInt(); status &= ~TX_INT; if (UART_IER_THRI & IER) @@ -225,7 +224,7 @@ Uart8250::write(PacketPtr pkt) status &= ~TX_INT; } - if ((UART_IER_RDI & IER) && term->dataAvailable()) { + if ((UART_IER_RDI & IER) && device->dataAvailable()) { DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n"); scheduleIntr(&rxIntrEvent); } else { |