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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-02-03 14:25:47 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-02-03 14:25:47 -0500 |
| commit | 851b29ad2077a886263be0973f58b84bea6641ab (patch) | |
| tree | 72f298eae475e7f97bb9e82cc8a77fb3ce8c409c /src/dev/virtio | |
| parent | b34b55b59772ec32cdd896de265b7b9ac7e7b839 (diff) | |
| download | gem5-851b29ad2077a886263be0973f58b84bea6641ab.tar.xz | |
dev: Correctly clear interrupts in VirtIO PCI
Correctly clear the PCI interrupt belonging to a VirtIO device when
the ISR register is read.
Diffstat (limited to 'src/dev/virtio')
| -rw-r--r-- | src/dev/virtio/pci.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/dev/virtio/pci.cc b/src/dev/virtio/pci.cc index a051a8f51..fb0735eba 100644 --- a/src/dev/virtio/pci.cc +++ b/src/dev/virtio/pci.cc @@ -123,8 +123,11 @@ PciVirtIO::read(PacketPtr pkt) case OFF_ISR_STATUS: { DPRINTF(VIOPci, " ISR_STATUS\n"); assert(size == sizeof(uint8_t)); - uint8_t isr_status(interruptDeliveryPending ? 1 : 0); - interruptDeliveryPending = false; + const uint8_t isr_status(interruptDeliveryPending ? 1 : 0); + if (interruptDeliveryPending) { + interruptDeliveryPending = false; + intrClear(); + } pkt->set<uint8_t>(isr_status); } break; |