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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-13 06:43:09 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-13 06:43:09 -0500
commit5a9a743cfc4517f93e5c94533efa767b92272c59 (patch)
treef3dbc078a51e5759b26b1a5f16263ddb1cf55a7b /src/dev/x86/Pc.py
parent8cb4a2208d568eb86ad3f6c6bb250bcbe2952302 (diff)
downloadgem5-5a9a743cfc4517f93e5c94533efa767b92272c59.tar.xz
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
Diffstat (limited to 'src/dev/x86/Pc.py')
-rw-r--r--src/dev/x86/Pc.py14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index bb8c91ac6..5b7d0864e 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -71,12 +71,12 @@ class Pc(Platform):
def attachIO(self, bus):
self.south_bridge.attachIO(bus)
- self.i_dont_exist.pio = bus.port
- self.behind_pci.pio = bus.port
- self.com_1.pio = bus.port
- self.fake_com_2.pio = bus.port
- self.fake_com_3.pio = bus.port
- self.fake_com_4.pio = bus.port
- self.fake_floppy.pio = bus.port
+ self.i_dont_exist.pio = bus.master
+ self.behind_pci.pio = bus.master
+ self.com_1.pio = bus.master
+ self.fake_com_2.pio = bus.master
+ self.fake_com_3.pio = bus.master
+ self.fake_com_4.pio = bus.master
+ self.fake_floppy.pio = bus.master
self.pciconfig.pio = bus.default
bus.use_default_range = True