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authorGabe Black <gblack@eecs.umich.edu>2008-10-11 02:21:44 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-11 02:21:44 -0700
commit826621eb1722eb557d4c24f79e110fbed09e5fb5 (patch)
tree23d0278aff2bc7615b31b074e8453019070d7126 /src/dev/x86/SConscript
parentbc2217eefc8db831b72dfdcae7ecc9bd95a31c3c (diff)
downloadgem5-826621eb1722eb557d4c24f79e110fbed09e5fb5.tar.xz
X86: Bring the South Bridge device into dev/x86 and get rid of south_bridge directory.
--HG-- rename : src/dev/x86/south_bridge/SouthBridge.py => src/dev/x86/SouthBridge.py rename : src/dev/x86/south_bridge/south_bridge.cc => src/dev/x86/south_bridge.cc rename : src/dev/x86/south_bridge/south_bridge.hh => src/dev/x86/south_bridge.hh
Diffstat (limited to 'src/dev/x86/SConscript')
-rw-r--r--src/dev/x86/SConscript3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index 0e2bf0be6..b71649fdd 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -34,6 +34,9 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
SimObject('PC.py')
Source('pc.cc')
+ SimObject('SouthBridge.py')
+ Source('south_bridge.cc')
+
SimObject('Cmos.py')
Source('cmos.cc')
TraceFlag('CMOS', 'Accesses to CMOS devices')