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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-04-05 11:09:19 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-04-05 11:09:19 -0500 |
| commit | 4f4a710457af4a9c8e72632995b55f106110ac9c (patch) | |
| tree | 816cc9af7167d0d016df34768fdf701ea5d3a140 /src/dev/x86/SouthBridge.py | |
| parent | f1a60906132fb816f80917d830b34df5e5d87ad4 (diff) | |
| download | gem5-4f4a710457af4a9c8e72632995b55f106110ac9c.tar.xz | |
Config: corrects the way Ruby attaches to the DMA ports
With recent changes to the memory system, a port cannot be assigned a peer
port twice. While making use of the Ruby memory system in FS mode, DMA
ports were assigned peer twice, once for the classic memory system
and once for the Ruby memory system. This patch removes this double
assignment of peer ports.
Diffstat (limited to 'src/dev/x86/SouthBridge.py')
| -rw-r--r-- | src/dev/x86/SouthBridge.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 9f7070e96..87f4c3798 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -85,7 +85,7 @@ class SouthBridge(SimObject): ide.InterruptLine = 14 ide.InterruptPin = 1 - def attachIO(self, bus): + def attachIO(self, bus, dma_ports): # Route interupt signals self.int_lines = \ [X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)), @@ -106,7 +106,8 @@ class SouthBridge(SimObject): self.dma1.pio = bus.master self.ide.pio = bus.master self.ide.config = bus.master - self.ide.dma = bus.slave + if dma_ports.count(self.ide.dma) == 0: + self.ide.dma = bus.slave self.keyboard.pio = bus.master self.pic1.pio = bus.master self.pic2.pio = bus.master |