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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-13 06:43:09 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-13 06:43:09 -0500 |
commit | 5a9a743cfc4517f93e5c94533efa767b92272c59 (patch) | |
tree | f3dbc078a51e5759b26b1a5f16263ddb1cf55a7b /src/dev/x86/SouthBridge.py | |
parent | 8cb4a2208d568eb86ad3f6c6bb250bcbe2952302 (diff) | |
download | gem5-5a9a743cfc4517f93e5c94533efa767b92272c59.tar.xz |
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.
Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
Diffstat (limited to 'src/dev/x86/SouthBridge.py')
-rw-r--r-- | src/dev/x86/SouthBridge.py | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index baff35e0b..9f7070e96 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -102,15 +102,15 @@ class SouthBridge(SimObject): self.speaker.i8254 = self.pit self.io_apic.external_int_pic = self.pic1 # Connect to the bus - self.cmos.pio = bus.port - self.dma1.pio = bus.port - self.ide.pio = bus.port - self.ide.config = bus.port - self.ide.dma = bus.port - self.keyboard.pio = bus.port - self.pic1.pio = bus.port - self.pic2.pio = bus.port - self.pit.pio = bus.port - self.speaker.pio = bus.port - self.io_apic.pio = bus.port - self.io_apic.int_port = bus.port + self.cmos.pio = bus.master + self.dma1.pio = bus.master + self.ide.pio = bus.master + self.ide.config = bus.master + self.ide.dma = bus.slave + self.keyboard.pio = bus.master + self.pic1.pio = bus.master + self.pic2.pio = bus.master + self.pit.pio = bus.master + self.speaker.pio = bus.master + self.io_apic.pio = bus.master + self.io_apic.int_master = bus.slave |