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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-08-21 05:50:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-08-21 05:50:03 -0400 |
| commit | 70e99e0b915fa7ed9ac682af6f68f077799ddea7 (patch) | |
| tree | f8554cd3a43fee7e246458b89ee52f5c67686f0c /src/dev/x86/SouthBridge.py | |
| parent | a81c969529d3a1645b490fcde93d231ec997b7ba (diff) | |
| download | gem5-70e99e0b915fa7ed9ac682af6f68f077799ddea7.tar.xz | |
Device: Remove overloaded pio_latency parameter
This patch removes the overloading of the parameter, which seems both
redundant, and possibly incorrect.
The PciConfigAll now also uses a Param.Latency rather than a
Param.Tick. For backwards compatibility it still sets the pio_latency
to 1 tick. All the comments have also been updated to not state that
it is in simticks when it is not necessarily the case.
Diffstat (limited to 'src/dev/x86/SouthBridge.py')
| -rw-r--r-- | src/dev/x86/SouthBridge.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 87f4c3798..7ac208d5e 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -45,7 +45,6 @@ def x86IOAddress(port): class SouthBridge(SimObject): type = 'SouthBridge' - pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") platform = Param.Platform(Parent.any, "Platform this device is part of") _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master') |