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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-26 02:09:54 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-26 02:09:54 -0700 |
| commit | 06b3e3c303599e4227212638fa4778d115842eea (patch) | |
| tree | fa55d4cc4058d9ddc87630603ef137856fe2a0c8 /src/dev/x86/i82094aa.hh | |
| parent | 2f34a7eaeb6d82b745fbd57fa4cc31d874ed202c (diff) | |
| download | gem5-06b3e3c303599e4227212638fa4778d115842eea.tar.xz | |
X86: Implement lowest priority interrupts more correctly.
Lowest priority interrupts are now delivered based on a rotating offset into
the list of potential recipients. There could be parasitic cases were a
processor gets picked on and ends up at that rotating offset all the time, but
it's much more likely that the group will stay consistent and the pain will be
distributed evenly.
Diffstat (limited to 'src/dev/x86/i82094aa.hh')
| -rw-r--r-- | src/dev/x86/i82094aa.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh index e81d85fa9..c3a832aa9 100644 --- a/src/dev/x86/i82094aa.hh +++ b/src/dev/x86/i82094aa.hh @@ -77,6 +77,8 @@ class I82094AA : public PioDevice, public IntDev uint8_t id; uint8_t arbId; + uint64_t lowestPriorityOffset; + static const uint8_t TableSize = 24; // This implementation is based on version 0x11, but 0x14 avoids having // to deal with the arbitration and APIC bus guck. |