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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-24 11:50:15 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-24 11:50:15 -0500 |
commit | 77878d0a87ee18709ca4d6459b8ae436cc101fa7 (patch) | |
tree | 2db1f5113fadae1d49d6ef5048f1706c1d31307c /src/dev/x86/intdev.cc | |
parent | 86c2aad482df4bf56977bf1a098d2dd01c641bfd (diff) | |
download | gem5-77878d0a87ee18709ca4d6459b8ae436cc101fa7.tar.xz |
MEM: Prepare mport for master/slave split
This patch simplifies the mport in preparation for a split into a
master and slave role for the message ports. In particular,
sendMessageAtomic was only used in a single location and similarly so
sendMessageTiming. The affected interrupt device is updated
accordingly.
Diffstat (limited to 'src/dev/x86/intdev.cc')
-rw-r--r-- | src/dev/x86/intdev.cc | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/dev/x86/intdev.cc b/src/dev/x86/intdev.cc index 23ec20b9a..bcfab5fe4 100644 --- a/src/dev/x86/intdev.cc +++ b/src/dev/x86/intdev.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2008 The Regents of The University of Michigan * All rights reserved. * @@ -31,17 +43,21 @@ #include "dev/x86/intdev.hh" void -X86ISA::IntDev::IntPort::sendMessage(ApicList apics, - TriggerIntMessage message, bool timing) +X86ISA::IntDev::IntPort::sendMessage(ApicList apics, TriggerIntMessage message, + bool timing) { ApicList::iterator apicIt; for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) { PacketPtr pkt = buildIntRequest(*apicIt, message); if (timing) { - sendMessageTiming(pkt, latency); + schedSendTiming(pkt, curTick() + latency); // The target handles cleaning up the packet in timing mode. } else { - sendMessageAtomic(pkt); + // ignore the latency involved in the atomic transaction + sendAtomic(pkt); + assert(pkt->isResponse()); + // also ignore the latency in handling the response + recvResponse(pkt); delete pkt->req; delete pkt; } |