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authorSteve Reinhardt <stever@gmail.com>2013-07-11 21:56:50 -0500
committerSteve Reinhardt <stever@gmail.com>2013-07-11 21:56:50 -0500
commit502ad1e6757116867e0e0529c0c080320a2b440b (patch)
tree7f2f79fd913a23a4cfc6bdb9a3147551e6624c00 /src/dev/x86/intdev.hh
parent2737650a69f0c56d325c2d9cfd45eef099fbd581 (diff)
downloadgem5-502ad1e6757116867e0e0529c0c080320a2b440b.tar.xz
dev: consistently end device classes in 'Device'
PciDev and IntDev stuck out as the only device classes that ended in 'Dev' rather than 'Device'. This patch takes care of that inconsistency. Note that you may need to delete pre-existing files matching build/*/python/m5/internal/param_* as scons does not pick up indirect dependencies on imported python modules when generating params, and the PciDev -> PciDevice rename takes place in a file (dev/Device.py) that gets imported quite a bit. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/dev/x86/intdev.hh')
-rw-r--r--src/dev/x86/intdev.hh18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index 99c361bae..078ea2b6f 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -60,16 +60,16 @@ namespace X86ISA {
typedef std::list<int> ApicList;
-class IntDev
+class IntDevice
{
protected:
class IntSlavePort : public MessageSlavePort
{
- IntDev * device;
+ IntDevice * device;
public:
IntSlavePort(const std::string& _name, MemObject* _parent,
- IntDev* dev) :
+ IntDevice* dev) :
MessageSlavePort(_name, _parent), device(dev)
{
}
@@ -89,11 +89,11 @@ class IntDev
class IntMasterPort : public MessageMasterPort
{
- IntDev* device;
+ IntDevice* device;
Tick latency;
public:
IntMasterPort(const std::string& _name, MemObject* _parent,
- IntDev* dev, Tick _latency) :
+ IntDevice* dev, Tick _latency) :
MessageMasterPort(_name, _parent), device(dev), latency(_latency)
{
}
@@ -112,12 +112,12 @@ class IntDev
IntMasterPort intMasterPort;
public:
- IntDev(MemObject * parent, Tick latency = 0) :
+ IntDevice(MemObject * parent, Tick latency = 0) :
intMasterPort(parent->name() + ".int_master", parent, this, latency)
{
}
- virtual ~IntDev()
+ virtual ~IntDevice()
{}
virtual void init();
@@ -163,7 +163,7 @@ class IntDev
class IntSinkPin : public SimObject
{
public:
- IntDev * device;
+ IntDevice * device;
int number;
typedef X86IntSinkPinParams Params;
@@ -175,7 +175,7 @@ class IntSinkPin : public SimObject
}
IntSinkPin(Params *p) : SimObject(p),
- device(dynamic_cast<IntDev *>(p->device)), number(p->number)
+ device(dynamic_cast<IntDevice *>(p->device)), number(p->number)
{
assert(device);
}