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author | Steve Reinhardt <stever@gmail.com> | 2008-03-25 10:04:52 -0400 |
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committer | Steve Reinhardt <stever@gmail.com> | 2008-03-25 10:04:52 -0400 |
commit | ba1f7d31e0f28d64df2fb03fe4b69182b9d3ff34 (patch) | |
tree | 33f52cbce6ac4fa332976d2a53977c7bde876c6b /src/dev/x86/south_bridge/sub_device.hh | |
parent | 29be31ce3139c36f596e6edafbd3d253ee2200b3 (diff) | |
parent | 93dd1978a7750ba7cce04ae4401f5c6689290038 (diff) | |
download | gem5-ba1f7d31e0f28d64df2fb03fe4b69182b9d3ff34.tar.xz |
Automated merge with ssh://daystrom.m5sim.org//repo/m5
--HG--
extra : convert_revision : 7922848bb1145bcb2ee07d672d21cfe2dd98fc03
Diffstat (limited to 'src/dev/x86/south_bridge/sub_device.hh')
-rw-r--r-- | src/dev/x86/south_bridge/sub_device.hh | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/src/dev/x86/south_bridge/sub_device.hh b/src/dev/x86/south_bridge/sub_device.hh new file mode 100644 index 000000000..3cc51bdd9 --- /dev/null +++ b/src/dev/x86/south_bridge/sub_device.hh @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__ +#define __DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__ + +#include "arch/x86/x86_traits.hh" +#include "base/range.hh" +#include "mem/packet.hh" + +namespace X86ISA +{ + +class SubDevice +{ + public: + + Range<Addr> addrRange; + Tick latency; + + virtual + ~SubDevice() + {} + + SubDevice() + {} + SubDevice(Tick _latency) : latency(_latency) + {} + SubDevice(Addr start, Addr size, Tick _latency) : + addrRange(RangeSize(x86IOAddress(start), size)), latency(_latency) + {} + + virtual Tick + read(PacketPtr pkt) + { + assert(pkt->getSize() <= 4); + pkt->allocate(); + const uint32_t neg1 = -1; + pkt->setData((uint8_t *)(&neg1)); + return latency; + } + + virtual Tick + write(PacketPtr pkt) + { + return latency; + } +}; + +}; // namespace X86ISA + +#endif //__DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__ |