diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:54:48 -0400 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:54:48 -0400 |
commit | 4f9a0402f629dbd78494bd7e820ffa41b0a5f245 (patch) | |
tree | 95083f875c9fe827509d47e4c484ec595f0fcf98 /src/dev/x86 | |
parent | 0368ccdedaa6b6fecb0f04924456953c92396188 (diff) | |
download | gem5-4f9a0402f629dbd78494bd7e820ffa41b0a5f245.tar.xz |
Dev: Seperate the 8254 timer from tsunami and use it in that and the PC.
Diffstat (limited to 'src/dev/x86')
-rw-r--r-- | src/dev/x86/south_bridge/i8254.cc | 30 | ||||
-rw-r--r-- | src/dev/x86/south_bridge/i8254.hh | 16 | ||||
-rw-r--r-- | src/dev/x86/south_bridge/south_bridge.cc | 4 |
3 files changed, 24 insertions, 26 deletions
diff --git a/src/dev/x86/south_bridge/i8254.cc b/src/dev/x86/south_bridge/i8254.cc index fb6723a51..7c3501c37 100644 --- a/src/dev/x86/south_bridge/i8254.cc +++ b/src/dev/x86/south_bridge/i8254.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004-2005 The Regents of The University of Michigan + * Copyright (c) 2008 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -38,21 +38,21 @@ X86ISA::I8254::read(PacketPtr pkt) switch(pkt->getAddr() - addrRange.start) { case 0x0: - warn("Reading from timer 0 counter.\n"); + pkt->set(pit.counter0.read()); break; case 0x1: - warn("Reading from timer 1 counter.\n"); + pkt->set(pit.counter1.read()); break; case 0x2: - warn("Reading from timer 2 counter.\n"); + pkt->set(pit.counter2.read()); break; case 0x3: - fatal("Reading from timer control word which is read only.\n"); + pkt->set(uint8_t(-1)); break; default: panic("Read from undefined i8254 register.\n"); } - return SubDevice::read(pkt); + return latency; } Tick @@ -62,25 +62,19 @@ X86ISA::I8254::write(PacketPtr pkt) switch(pkt->getAddr() - addrRange.start) { case 0x0: - warn("Writing to timer 0 counter.\n"); + pit.counter0.write(pkt->get<uint8_t>()); break; case 0x1: - warn("Writing to timer 1 counter.\n"); + pit.counter1.write(pkt->get<uint8_t>()); break; case 0x2: - warn("Writing to timer 2 counter.\n"); + pit.counter2.write(pkt->get<uint8_t>()); break; case 0x3: - processControlWord(pkt->get<uint8_t>()); - return latency; + pit.writeControl(pkt->get<uint8_t>()); + break; default: panic("Write to undefined i8254 register.\n"); } - return SubDevice::write(pkt); -} - -void -X86ISA::I8254::processControlWord(uint8_t word) -{ - warn("I8254 received control word %x.\n", word); + return latency; } diff --git a/src/dev/x86/south_bridge/i8254.hh b/src/dev/x86/south_bridge/i8254.hh index f246fd8e4..519049e93 100644 --- a/src/dev/x86/south_bridge/i8254.hh +++ b/src/dev/x86/south_bridge/i8254.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004-2005 The Regents of The University of Michigan + * Copyright (c) 2008 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -33,24 +33,28 @@ #include "arch/x86/x86_traits.hh" #include "base/range.hh" +#include "dev/intel_8254_timer.hh" #include "dev/x86/south_bridge/sub_device.hh" +#include <string> + namespace X86ISA { class I8254 : public SubDevice { protected: - void processControlWord(uint8_t word); + Intel8254Timer pit; public: - I8254() + I8254(const std::string &name) : pit(name) {} - I8254(Tick _latency) : SubDevice(_latency) + I8254(const std::string &name, Tick _latency) : + SubDevice(_latency), pit(name) {} - I8254(Addr start, Addr size, Tick _latency) : - SubDevice(start, size, _latency) + I8254(const std::string &name, Addr start, Addr size, Tick _latency) : + SubDevice(start, size, _latency), pit(name) {} Tick read(PacketPtr pkt); diff --git a/src/dev/x86/south_bridge/south_bridge.cc b/src/dev/x86/south_bridge/south_bridge.cc index f25b3b811..cc20ea09e 100644 --- a/src/dev/x86/south_bridge/south_bridge.cc +++ b/src/dev/x86/south_bridge/south_bridge.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004-2005 The Regents of The University of Michigan + * Copyright (c) 2008 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -68,7 +68,7 @@ SouthBridge::write(PacketPtr pkt) SouthBridge::SouthBridge(const Params *p) : PioDevice(p), pic1(0x20, 2, p->pio_latency), pic2(0xA0, 2, p->pio_latency), - pit(0x40, 4, p->pio_latency), + pit(p->name + ".pit", 0x40, 4, p->pio_latency), cmos(0x70, 2, p->pio_latency), speaker(0x61, 1, p->pio_latency) { |