dev: Rewrite PCI host functionality

The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

  * Configurable configuration space decoding. The number of bits
    dedicated to a device is a prameter, making it possible to support
    both CAM, ECAM, and legacy mappings.

  * Basic interrupt mapping using the interruptLine value from a
    device's configuration space. This behavior is the same as in the
    old implementation. More advanced controllers can override the
    interrupt mapping method to dynamically assign host interrupts to
    PCI devices.

  * Simple (base + addr) remapping from the PCI bus's address space to
    physical addresses for PIO, memory, and DMA.

4 files changed, 14 insertions, 68 deletions

diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 8740159c4..3100f59b7 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -30,24 +30,29 @@ from m5.params import *
 from m5.proxy import *
 
 from Device import IsaFake
-from Pci import PciConfigAll
 from Platform import Platform
 from SouthBridge import SouthBridge
 from Terminal import Terminal
 from Uart import Uart8250
+from PciHost import GenericPciHost
 
 def x86IOAddress(port):
     IO_address_space_base = 0x8000000000000000
     return IO_address_space_base + port;
 
+class PcPciHost(GenericPciHost):
+    conf_base = 0xC000000000000000
+    conf_size = "16MB"
+
+    pci_pio_base = 0x8000000000000000
+
 class Pc(Platform):
     type = 'Pc'
     cxx_header = "dev/x86/pc.hh"
     system = Param.System(Parent.any, "system")
 
-    pciconfig = PciConfigAll()
-
     south_bridge = SouthBridge()
+    pci_host = PcPciHost()
 
     # "Non-existant" ports used for timing purposes by the linux kernel
     i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
@@ -80,4 +85,4 @@ class Pc(Platform):
         self.fake_com_3.pio = bus.master
         self.fake_com_4.pio = bus.master
         self.fake_floppy.pio = bus.master
-        self.pciconfig.pio = bus.default
+        self.pci_host.pio = bus.default
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 911853dd5..704656594 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -106,7 +106,6 @@ class SouthBridge(SimObject):
         self.cmos.pio = bus.master
         self.dma1.pio = bus.master
         self.ide.pio = bus.master
-        self.ide.config = bus.master
         if dma_ports.count(self.ide.dma) == 0:
                 self.ide.dma = bus.slave
         self.keyboard.pio = bus.master
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index dd8e34d9e..fe3119803 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -141,33 +141,6 @@ Pc::clearPciInt(int line)
     warn_once("Tried to clear PCI interrupt %d\n", line);
 }
 
-Addr
-Pc::pciToDma(Addr pciAddr) const
-{
-    return pciAddr;
-}
-
-Addr
-Pc::calcPciConfigAddr(int bus, int dev, int func)
-{
-    assert(func < 8);
-    assert(dev < 32);
-    assert(bus == 0);
-    return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
-}
-
-Addr
-Pc::calcPciIOAddr(Addr addr)
-{
-    return PhysAddrPrefixIO + addr;
-}
-
-Addr
-Pc::calcPciMemAddr(Addr addr)
-{
-    return addr;
-}
-
 Pc *
 PcParams::create()
 {
diff --git a/src/dev/x86/pc.hh b/src/dev/x86/pc.hh
index c999440d2..6cc57cb5d 100644
--- a/src/dev/x86/pc.hh
+++ b/src/dev/x86/pc.hh
@@ -61,43 +61,12 @@ class Pc : public Platform
 
     Pc(const Params *p);
 
-    /**
-     * Cause the cpu to post a serial interrupt to the CPU.
-     */
-    virtual void postConsoleInt();
-
-    /**
-     * Clear a posted CPU interrupt
-     */
-    virtual void clearConsoleInt();
-
-    /**
-     * Cause the chipset to post a pci interrupt to the CPU.
-     */
-    virtual void postPciInt(int line);
-
-    /**
-     * Clear a posted PCI->CPU interrupt
-     */
-    virtual void clearPciInt(int line);
-
-
-    virtual Addr pciToDma(Addr pciAddr) const;
-
-    /**
-     * Calculate the configuration address given a bus/dev/func.
-     */
-    virtual Addr calcPciConfigAddr(int bus, int dev, int func);
-
-    /**
-     * Calculate the address for an IO location on the PCI bus.
-     */
-    virtual Addr calcPciIOAddr(Addr addr);
+  public:
+    void postConsoleInt() override;
+    void clearConsoleInt() override;
 
-    /**
-     * Calculate the address for a memory location on the PCI bus.
-     */
-    virtual Addr calcPciMemAddr(Addr addr);
+    void postPciInt(int line) override;
+    void clearPciInt(int line) override;
 };
 
 #endif // __DEV_PC_HH__