sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.

11 files changed, 13 insertions, 0 deletions

diff --git a/src/dev/x86/Cmos.py b/src/dev/x86/Cmos.py
index 266fb8937..c0b2be58a 100644
--- a/src/dev/x86/Cmos.py
+++ b/src/dev/x86/Cmos.py
@@ -34,6 +34,7 @@ from X86IntPin import X86IntSourcePin
 class Cmos(BasicPioDevice):
     type = 'Cmos'
     cxx_class='X86ISA::Cmos'
+    cxx_header = "dev/x86/cmos.hh"
     time = Param.Time('01/01/2012',
         "System time to use ('Now' for actual time)")
     int_pin = Param.X86IntSourcePin(X86IntSourcePin(),
diff --git a/src/dev/x86/I8042.py b/src/dev/x86/I8042.py
index 57bf32ca0..d13a13341 100644
--- a/src/dev/x86/I8042.py
+++ b/src/dev/x86/I8042.py
@@ -34,6 +34,7 @@ from X86IntPin import X86IntSourcePin
 class I8042(BasicPioDevice):
     type = 'I8042'
     cxx_class = 'X86ISA::I8042'
+    cxx_header = "dev/x86/i8042.hh"
     # This isn't actually used for anything here.
     pio_addr = 0x0
     data_port = Param.Addr('Data port address')
diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
index 3b076a9d6..7e71cdfc1 100644
--- a/src/dev/x86/I82094AA.py
+++ b/src/dev/x86/I82094AA.py
@@ -34,6 +34,7 @@ from X86IntPin import X86IntSinkPin
 class I82094AA(BasicPioDevice):
     type = 'I82094AA'
     cxx_class = 'X86ISA::I82094AA'
+    cxx_header = "dev/x86/i82094aa.hh"
     apic_id = Param.Int(1, 'APIC id for this IO APIC')
     int_master = MasterPort("Port for sending interrupt messages")
     int_latency = Param.Latency('1ns', \
diff --git a/src/dev/x86/I8237.py b/src/dev/x86/I8237.py
index 0121c3d24..a4c5e3ad5 100644
--- a/src/dev/x86/I8237.py
+++ b/src/dev/x86/I8237.py
@@ -33,3 +33,4 @@ from Device import BasicPioDevice
 class I8237(BasicPioDevice):
     type = 'I8237'
     cxx_class = 'X86ISA::I8237'
+    cxx_header = "dev/x86/i8237.hh"
diff --git a/src/dev/x86/I8254.py b/src/dev/x86/I8254.py
index 6fdcb1c8d..574dd81c2 100644
--- a/src/dev/x86/I8254.py
+++ b/src/dev/x86/I8254.py
@@ -34,5 +34,6 @@ from X86IntPin import X86IntSourcePin
 class I8254(BasicPioDevice):
     type = 'I8254'
     cxx_class = 'X86ISA::I8254'
+    cxx_header = "dev/x86/i8254.hh"
     int_pin = Param.X86IntSourcePin(X86IntSourcePin(),
             'Pin to signal timer interrupts to')
diff --git a/src/dev/x86/I8259.py b/src/dev/x86/I8259.py
index 30ea14225..4403c3f53 100644
--- a/src/dev/x86/I8259.py
+++ b/src/dev/x86/I8259.py
@@ -40,6 +40,7 @@ class X86I8259CascadeMode(Enum):
 class I8259(BasicPioDevice):
     type = 'I8259'
     cxx_class='X86ISA::I8259'
+    cxx_header = "dev/x86/i8259.hh"
     output = Param.X86IntSourcePin(X86IntSourcePin(),
             'The pin this I8259 drives')
     mode = Param.X86I8259CascadeMode('How this I8259 is cascaded')
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 91292788c..3fc2382b7 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -42,6 +42,7 @@ def x86IOAddress(port):
 
 class Pc(Platform):
     type = 'Pc'
+    cxx_header = "dev/x86/pc.hh"
     system = Param.System(Parent.any, "system")
 
     pciconfig = PciConfigAll()
diff --git a/src/dev/x86/PcSpeaker.py b/src/dev/x86/PcSpeaker.py
index cc1f5517a..f1c23157b 100644
--- a/src/dev/x86/PcSpeaker.py
+++ b/src/dev/x86/PcSpeaker.py
@@ -33,4 +33,5 @@ from Device import BasicPioDevice
 class PcSpeaker(BasicPioDevice):
     type = 'PcSpeaker'
     cxx_class = 'X86ISA::Speaker'
+    cxx_header = "dev/x86/speaker.hh"
     i8254 = Param.I8254('Timer that drives the speaker')
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 7ac208d5e..45c49ce3a 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -45,6 +45,7 @@ def x86IOAddress(port):
 
 class SouthBridge(SimObject):
     type = 'SouthBridge'
+    cxx_header = "dev/x86/south_bridge.hh"
     platform = Param.Platform(Parent.any, "Platform this device is part of")
 
     _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
diff --git a/src/dev/x86/X86IntPin.py b/src/dev/x86/X86IntPin.py
index 35e274624..53760b496 100644
--- a/src/dev/x86/X86IntPin.py
+++ b/src/dev/x86/X86IntPin.py
@@ -33,11 +33,13 @@ from m5.SimObject import SimObject
 class X86IntSourcePin(SimObject):
     type = 'X86IntSourcePin'
     cxx_class = 'X86ISA::IntSourcePin'
+    cxx_header = "dev/x86/intdev.hh"
 
 # A generic pin to receive an interrupt signal generated by another device.
 class X86IntSinkPin(SimObject):
     type = 'X86IntSinkPin'
     cxx_class = 'X86ISA::IntSinkPin'
+    cxx_header = "dev/x86/intdev.hh"
 
     device = Param.SimObject("Device this pin belongs to")
     number = Param.Int("The pin number on the device")
@@ -46,6 +48,7 @@ class X86IntSinkPin(SimObject):
 class X86IntLine(SimObject):
     type = 'X86IntLine'
     cxx_class = 'X86ISA::IntLine'
+    cxx_header = "dev/x86/intdev.hh"
 
     source = Param.X86IntSourcePin("Pin driving this line")
     sink = Param.X86IntSinkPin("Pin driven by this line")
diff --git a/src/dev/x86/speaker.hh b/src/dev/x86/speaker.hh
index 5aa1ccf0a..2886a76d7 100644
--- a/src/dev/x86/speaker.hh
+++ b/src/dev/x86/speaker.hh
@@ -32,6 +32,7 @@
 #define __DEV_X86_SPEAKER_HH__
 
 #include "base/bitunion.hh"
+#include "dev/io_device.hh"
 #include "params/PcSpeaker.hh"
 
 namespace X86ISA