X86: Create an IO APIC device.

8 files changed, 369 insertions, 1 deletions

diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
new file mode 100644
index 000000000..731d831f0
--- /dev/null
+++ b/src/dev/x86/I82094AA.py
@@ -0,0 +1,41 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Device import BasicPioDevice
+from X86IntPin import X86IntPin
+
+class I82094AA(BasicPioDevice):
+    type = 'I82094AA'
+    cxx_class = 'X86ISA::I82094AA'
+    pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
+    pio_addr = Param.Addr("Device address")
+
+    def pin(self, line):
+        return X86IntPin(device=self, line=line)
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index 7e3cc6eff..3481235c6 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -53,5 +53,9 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
     Source('speaker.cc')
     TraceFlag('PcSpeaker')
 
+    SimObject('I82094AA.py')
+    Source('i82094aa.cc')
+    TraceFlag('I82094AA')
+
     SimObject('X86IntPin.py')
     Source('intdev.cc')
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 2f4b8438a..15ffe153f 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -29,6 +29,7 @@
 from m5.params import *
 from m5.proxy import *
 from Cmos import Cmos
+from I82094AA import I82094AA
 from I8254 import I8254
 from I8259 import I8259
 from PcSpeaker import PcSpeaker
@@ -48,15 +49,18 @@ class SouthBridge(SimObject):
     _cmos = Cmos(pio_addr=x86IOAddress(0x70))
     _pit = I8254(pio_addr=x86IOAddress(0x40))
     _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
+    _io_apic = I82094AA(pio_addr=0xFEC00000)
 
     pic1 = Param.I8259(_pic1, "Master PIC")
     pic2 = Param.I8259(_pic2, "Slave PIC")
     cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
     pit = Param.I8254(_pit, "Programmable interval timer")
     speaker = Param.PcSpeaker(_speaker, "PC speaker")
+    io_apic = Param.I82094AA(_io_apic, "I/O APIC")
 
     def attachIO(self, bus):
         # Make internal connections
+        self.pic1.output = self.io_apic.pin(0)
         self.pic2.output = self.pic1.pin(2)
         self.cmos.int_pin = self.pic2.pin(0)
         self.pit.int_pin = self.pic1.pin(0)
@@ -67,3 +71,4 @@ class SouthBridge(SimObject):
         self.pic2.pio = bus.port
         self.pit.pio = bus.port
         self.speaker.pio = bus.port
+        self.io_apic.pio = bus.port
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
new file mode 100644
index 000000000..713f59592
--- /dev/null
+++ b/src/dev/x86/i82094aa.cc
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/i82094aa.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "sim/system.hh"
+
+X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p),
+   latency(p->pio_latency), pioAddr(p->pio_addr)
+{
+    // This assumes there's only one I/O APIC in the system
+    id = sys->getNumCPUs();
+    assert(id <= 0xf);
+    arbId = id;
+    regSel = 0;
+    memset(redirTable, 0, sizeof(RedirTableEntry) * TableSize);
+}
+
+Tick
+X86ISA::I82094AA::read(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 4);
+    Addr offset = pkt->getAddr() - pioAddr;
+    switch(offset) {
+      case 0:
+        pkt->set<uint32_t>(regSel);
+        break;
+      case 16:
+        pkt->set<uint32_t>(readReg(regSel));
+        break;
+      default:
+        panic("Illegal read from I/O APIC.\n");
+    }
+    return latency;
+}
+
+Tick
+X86ISA::I82094AA::write(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 4);
+    Addr offset = pkt->getAddr() - pioAddr;
+    switch(offset) {
+      case 0:
+        regSel = pkt->get<uint32_t>();
+        break;
+      case 16:
+        writeReg(regSel, pkt->get<uint32_t>());
+        break;
+      default:
+        panic("Illegal write to I/O APIC.\n");
+    }
+    return latency;
+}
+
+void
+X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
+{
+    if (offset == 0x0) {
+        id = bits(value, 27, 24);
+    } else if (offset == 0x1) {
+        // The IOAPICVER register is read only.
+    } else if (offset == 0x2) {
+        arbId = bits(value, 27, 24);
+    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
+        int index = (offset - 0x10) / 2;
+        if (offset % 2) {
+            redirTable[index].topDW = value;
+            redirTable[index].topReserved = 0;
+        } else {
+            redirTable[index].bottomDW = value;
+            redirTable[index].bottomReserved = 0;
+        }
+    } else {
+        warn("Access to undefined I/O APIC register %#x.\n", offset);
+    }
+    DPRINTF(I82094AA,
+            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
+}
+
+uint32_t
+X86ISA::I82094AA::readReg(uint8_t offset)
+{
+    uint32_t result = 0;
+    if (offset == 0x0) {
+        result = id << 24;
+    } else if (offset == 0x1) {
+        result = ((TableSize - 1) << 16) | APICVersion;
+    } else if (offset == 0x2) {
+        result = arbId << 24;
+    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
+        int index = (offset - 0x10) / 2;
+        if (offset % 2) {
+            result = redirTable[index].topDW;
+        } else {
+            result = redirTable[index].bottomDW;
+        }
+    } else {
+        warn("Access to undefined I/O APIC register %#x.\n", offset);
+    }
+    DPRINTF(I82094AA,
+            "Read %#x from I/O APIC register %#x.\n", result, offset);
+    return result;
+}
+
+void
+X86ISA::I82094AA::signalInterrupt(int line)
+{
+    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
+    assert(line < TableSize);
+    RedirTableEntry entry = redirTable[line];
+    if (entry.mask) {
+        DPRINTF(I82094AA, "Entry was masked.\n");
+        return;
+    } else {
+        if (entry.destMode == 0) {
+            DPRINTF(I82094AA,
+                    "Would send interrupt to APIC ID %d.\n", entry.dest);
+        } else {
+            DPRINTF(I82094AA, "Would send interrupts to APIC IDs:"
+                    "%s%s%s%s%s%s%s%s\n",
+                    bits((int)entry.dest, 0) ? " 0": "",
+                    bits((int)entry.dest, 1) ? " 1": "",
+                    bits((int)entry.dest, 2) ? " 2": "",
+                    bits((int)entry.dest, 3) ? " 3": "",
+                    bits((int)entry.dest, 4) ? " 4": "",
+                    bits((int)entry.dest, 5) ? " 5": "",
+                    bits((int)entry.dest, 6) ? " 6": "",
+                    bits((int)entry.dest, 7) ? " 7": ""
+                    );
+        }
+        switch(entry.deliveryMode) {
+          case 0:
+            DPRINTF(I82094AA, "Delivery mode is: Fixed.\n");
+            break;
+          case 1:
+            DPRINTF(I82094AA, "Delivery mode is: Lowest Priority.\n");
+            break;
+          case 2:
+            DPRINTF(I82094AA, "Delivery mode is: SMI.\n");
+            break;
+          case 3:
+            fatal("Tried to use reserved delivery mode "
+                    "for IO APIC entry %d.\n", line);
+            break;
+          case 4:
+            DPRINTF(I82094AA, "Delivery mode is: NMI.\n");
+            break;
+          case 5:
+            DPRINTF(I82094AA, "Delivery mode is: INIT.\n");
+            break;
+          case 6:
+            fatal("Tried to use reserved delivery mode "
+                    "for IO APIC entry %d.\n", line);
+            break;
+          case 7:
+            DPRINTF(I82094AA, "Delivery mode is: ExtINT.\n");
+            break;
+        }
+        DPRINTF(I82094AA, "Vector is %#x.\n", entry.vector);
+    }
+}
+
+X86ISA::I82094AA *
+I82094AAParams::create()
+{
+    return new X86ISA::I82094AA(this);
+}
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
new file mode 100644
index 000000000..b442e3e92
--- /dev/null
+++ b/src/dev/x86/i82094aa.hh
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_I82094AA_HH__
+#define __DEV_X86_I82094AA_HH__
+
+#include "base/bitunion.hh"
+#include "base/range_map.hh"
+#include "dev/io_device.hh"
+#include "dev/x86/intdev.hh"
+#include "params/I82094AA.hh"
+
+namespace X86ISA
+{
+
+class I82094AA : public PioDevice, public IntDev
+{
+  public:
+    BitUnion64(RedirTableEntry)
+        Bitfield<63, 32> topDW;
+        Bitfield<55, 32> topReserved;
+        Bitfield<31, 0> bottomDW;
+        Bitfield<31, 17> bottomReserved;
+        Bitfield<63, 56> dest;
+        Bitfield<16> mask;
+        Bitfield<15> trigger;
+        Bitfield<14> remoteIRR;
+        Bitfield<13> polarity;
+        Bitfield<12> deliveryStatus;
+        Bitfield<11> destMode;
+        Bitfield<10, 8> deliveryMode;
+        Bitfield<7, 0> vector;
+    EndBitUnion(RedirTableEntry)
+
+  protected:
+    Tick latency;
+    Addr pioAddr;
+
+    uint8_t regSel;
+    uint8_t id;
+    uint8_t arbId;
+
+    static const uint8_t TableSize = 24;
+    // This implementation is based on version 0x11, but 0x14 avoids having
+    // to deal with the arbitration and APIC bus guck.
+    static const uint8_t APICVersion = 0x14;
+
+    RedirTableEntry redirTable[TableSize];
+
+  public:
+    typedef I82094AAParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    I82094AA(Params *p);
+
+    Tick read(PacketPtr pkt);
+    Tick write(PacketPtr pkt);
+
+    void addressRanges(AddrRangeList &range_list)
+    {
+        range_list.clear();
+        range_list.push_back(RangeEx(pioAddr, pioAddr + 4));
+        range_list.push_back(RangeEx(pioAddr + 16, pioAddr + 20));
+    }
+
+    void writeReg(uint8_t offset, uint32_t value);
+    uint32_t readReg(uint8_t offset);
+
+    void signalInterrupt(int line);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index 0dc8d6cd5..4cd81dd50 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -39,6 +39,7 @@
 #include "arch/x86/x86_traits.hh"
 #include "cpu/intr_control.hh"
 #include "dev/terminal.hh"
+#include "dev/x86/i82094aa.hh"
 #include "dev/x86/i8254.hh"
 #include "dev/x86/pc.hh"
 #include "dev/x86/south_bridge.hh"
@@ -59,6 +60,10 @@ void
 Pc::init()
 {
     assert(southBridge);
+
+    /*
+     * Initialize the timer.
+     */
     I8254 & timer = *southBridge->pit;
     //Timer 0, mode 2, no bcd, 16 bit count
     timer.writeControl(0x34);
@@ -67,6 +72,16 @@ Pc::init()
     //Write a 16 bit count of 0
     timer.writeCounter(0, 0);
     timer.writeCounter(0, 0);
+
+    /*
+     * Initialize the I/O APIC.
+     */
+    I82094AA & ioApic = *southBridge->ioApic;
+    I82094AA::RedirTableEntry entry = 0;
+    entry.deliveryMode = 0x7;
+    entry.vector = 0x20;
+    ioApic.writeReg(0x10, entry.bottomDW);
+    ioApic.writeReg(0x11, entry.topDW);
 }
 
 Tick
diff --git a/src/dev/x86/south_bridge.cc b/src/dev/x86/south_bridge.cc
index d366de4ad..c456f478d 100644
--- a/src/dev/x86/south_bridge.cc
+++ b/src/dev/x86/south_bridge.cc
@@ -37,7 +37,7 @@ using namespace X86ISA;
 
 SouthBridge::SouthBridge(const Params *p) : SimObject(p),
     platform(p->platform), pit(p->pit), pic1(p->pic1), pic2(p->pic2),
-    cmos(p->cmos), speaker(p->speaker)
+    cmos(p->cmos), speaker(p->speaker), ioApic(p->io_apic)
 {
     // Let the platform know where we are
     Pc * pc = dynamic_cast<Pc *>(platform);
diff --git a/src/dev/x86/south_bridge.hh b/src/dev/x86/south_bridge.hh
index 5677aa8a0..61d6d387a 100644
--- a/src/dev/x86/south_bridge.hh
+++ b/src/dev/x86/south_bridge.hh
@@ -40,6 +40,7 @@ namespace X86ISA
     class I8259;
     class Cmos;
     class Speaker;
+    class I82094AA;
 }
 
 class SouthBridge : public SimObject
@@ -53,6 +54,7 @@ class SouthBridge : public SimObject
     X86ISA::I8259 * pic2;
     X86ISA::Cmos * cmos;
     X86ISA::Speaker * speaker;
+    X86ISA::I82094AA * ioApic;
 
   public:
     typedef SouthBridgeParams Params;