MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.

5 files changed, 22 insertions, 22 deletions

diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
index d4ab2cb17..09923f6c2 100644
--- a/src/dev/x86/I82094AA.py
+++ b/src/dev/x86/I82094AA.py
@@ -37,7 +37,7 @@ class I82094AA(BasicPioDevice):
     apic_id = Param.Int(1, 'APIC id for this IO APIC')
     pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
     pio_addr = Param.Addr("Device address")
-    int_port = Port("Port for sending and receiving interrupt messages")
+    int_master = MasterPort("Port for sending interrupt messages")
     int_latency = Param.Latency('1ns', \
             "Latency for an interrupt to propagate through this device.")
     external_int_pic = Param.I8259(NULL, "External PIC, if any")
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index bb8c91ac6..5b7d0864e 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -71,12 +71,12 @@ class Pc(Platform):
 
     def attachIO(self, bus):
         self.south_bridge.attachIO(bus)
-        self.i_dont_exist.pio = bus.port
-        self.behind_pci.pio = bus.port
-        self.com_1.pio = bus.port
-        self.fake_com_2.pio = bus.port
-        self.fake_com_3.pio = bus.port
-        self.fake_com_4.pio = bus.port
-        self.fake_floppy.pio = bus.port
+        self.i_dont_exist.pio = bus.master
+        self.behind_pci.pio = bus.master
+        self.com_1.pio = bus.master
+        self.fake_com_2.pio = bus.master
+        self.fake_com_3.pio = bus.master
+        self.fake_com_4.pio = bus.master
+        self.fake_floppy.pio = bus.master
         self.pciconfig.pio = bus.default
         bus.use_default_range = True
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index baff35e0b..9f7070e96 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -102,15 +102,15 @@ class SouthBridge(SimObject):
         self.speaker.i8254 = self.pit
         self.io_apic.external_int_pic = self.pic1
         # Connect to the bus
-        self.cmos.pio = bus.port
-        self.dma1.pio = bus.port
-        self.ide.pio = bus.port
-        self.ide.config = bus.port
-        self.ide.dma = bus.port
-        self.keyboard.pio = bus.port
-        self.pic1.pio = bus.port
-        self.pic2.pio = bus.port
-        self.pit.pio = bus.port
-        self.speaker.pio = bus.port
-        self.io_apic.pio = bus.port
-        self.io_apic.int_port = bus.port
+        self.cmos.pio = bus.master
+        self.dma1.pio = bus.master
+        self.ide.pio = bus.master
+        self.ide.config = bus.master
+        self.ide.dma = bus.slave
+        self.keyboard.pio = bus.master
+        self.pic1.pio = bus.master
+        self.pic2.pio = bus.master
+        self.pit.pio = bus.master
+        self.speaker.pio = bus.master
+        self.io_apic.pio = bus.master
+        self.io_apic.int_master = bus.slave
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index dfef059c3..60ef27012 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -123,7 +123,7 @@ class I82094AA : public PioDevice, public IntDev
 
     Port *getPort(const std::string &if_name, int idx = -1)
     {
-        if (if_name == "int_port")
+        if (if_name == "int_master")
             return intPort;
         return PioDevice::getPort(if_name, idx);
     }
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index 9713d042b..05b4d12a1 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -90,7 +90,7 @@ class IntDev
     IntDev(MemObject * parent, Tick latency = 0)
     {
         if (parent != NULL) {
-            intPort = new IntPort(parent->name() + ".int_port",
+            intPort = new IntPort(parent->name() + ".int_master",
                     parent, this, latency);
         } else {
             intPort = NULL;