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authorAdrien Pesle <adrien.pesle@arm.com>2018-10-12 12:42:33 +0200
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-10-17 14:47:14 +0000
commite086e74a79df938351a742c0eaebff602c4ad97d (patch)
tree6bbce775be769190455e5885029e7b592ca27c3b /src/dev
parent9181c2ea16d384c57e6bb4e757ecaf1b52b8e7f1 (diff)
downloadgem5-e086e74a79df938351a742c0eaebff602c4ad97d.tar.xz
dev-arm: Don't panic when EOIR a non active PPI
GIC architecture specification says that writing EOIR with a not active irq it is an unpredictable behavior. So, just warn when it happens for a PPI case, like it is already done in SPI case. Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13556 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev')
-rw-r--r--src/dev/arm/gic_v2.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index a24e56391..293c72f1f 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -601,7 +601,7 @@ GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
} else if (iar.ack_id < (SGI_MAX + PPI_MAX) ) {
uint32_t int_num = 1 << (iar.ack_id - SGI_MAX);
if (!(cpuPpiActive[ctx] & int_num))
- panic("CPU %d Done handling a PPI interrupt "
+ warn("CPU %d Done handling a PPI interrupt "
"that isn't active?\n", ctx);
cpuPpiActive[ctx] &= ~int_num;
} else {