MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.

10 files changed, 150 insertions, 150 deletions

diff --git a/src/dev/Device.py b/src/dev/Device.py
index c32946277..96c95ebc9 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -33,7 +33,7 @@ from MemObject import MemObject
 class PioDevice(MemObject):
     type = 'PioDevice'
     abstract = True
-    pio = Port("Programmed I/O port")
+    pio = SlavePort("Programmed I/O port")
     system = Param.System(Parent.any, "System this device is part of")
 
 class BasicPioDevice(PioDevice):
@@ -45,7 +45,7 @@ class BasicPioDevice(PioDevice):
 class DmaDevice(PioDevice):
     type = 'DmaDevice'
     abstract = True
-    dma = Port("DMA port")
+    dma = MasterPort("DMA port")
     min_backoff_delay = Param.Latency('4ns',
       "min time between a nack packet being received and the next request made by the device")
     max_backoff_delay = Param.Latency('10us',
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index 539e4ea9b..91d4e230e 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -37,8 +37,8 @@ class EtherObject(SimObject):
 
 class EtherLink(EtherObject):
     type = 'EtherLink'
-    int0 = Port("interface 0")
-    int1 = Port("interface 1")
+    int0 = SlavePort("interface 0")
+    int1 = SlavePort("interface 1")
     delay = Param.Latency('0us', "packet transmit delay")
     delay_var = Param.Latency('0ns', "packet transmit delay variability")
     speed = Param.NetworkBandwidth('1Gbps', "link speed")
@@ -64,7 +64,7 @@ class EtherDump(SimObject):
 class EtherDevice(PciDevice):
     type = 'EtherDevice'
     abstract = True
-    interface = Port("Ethernet Interface")
+    interface = MasterPort("Ethernet Interface")
 
 class IGbE(EtherDevice):
     # Base class for two IGbE adapters listed above
diff --git a/src/dev/Pci.py b/src/dev/Pci.py
index 95cb3916f..c866f9386 100644
--- a/src/dev/Pci.py
+++ b/src/dev/Pci.py
@@ -43,7 +43,7 @@ class PciDevice(DmaDevice):
     type = 'PciDevice'
     abstract = True
     platform = Param.Platform(Parent.any, "Platform this device is part of.")
-    config = Port("PCI configuration space port")
+    config = SlavePort("PCI configuration space port")
     pci_bus = Param.Int("PCI bus")
     pci_dev = Param.Int("PCI device number")
     pci_func = Param.Int("PCI function code")
diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py
index e6a899604..9a3ec0593 100644
--- a/src/dev/alpha/Tsunami.py
+++ b/src/dev/alpha/Tsunami.py
@@ -93,30 +93,30 @@ class Tsunami(Platform):
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-        self.cchip.pio = bus.port
-        self.pchip.pio = bus.port
+        self.cchip.pio = bus.master
+        self.pchip.pio = bus.master
         self.pciconfig.pio = bus.default
         bus.use_default_range = True
-        self.fake_sm_chip.pio = bus.port
-        self.fake_uart1.pio = bus.port
-        self.fake_uart2.pio = bus.port
-        self.fake_uart3.pio = bus.port
-        self.fake_uart4.pio = bus.port
-        self.fake_ppc.pio = bus.port
-        self.fake_OROM.pio = bus.port
-        self.fake_pnp_addr.pio = bus.port
-        self.fake_pnp_write.pio = bus.port
-        self.fake_pnp_read0.pio = bus.port
-        self.fake_pnp_read1.pio = bus.port
-        self.fake_pnp_read2.pio = bus.port
-        self.fake_pnp_read3.pio = bus.port
-        self.fake_pnp_read4.pio = bus.port
-        self.fake_pnp_read5.pio = bus.port
-        self.fake_pnp_read6.pio = bus.port
-        self.fake_pnp_read7.pio = bus.port
-        self.fake_ata0.pio = bus.port
-        self.fake_ata1.pio = bus.port
-        self.fb.pio = bus.port
-        self.io.pio = bus.port
-        self.uart.pio = bus.port
-        self.backdoor.pio = bus.port
+        self.fake_sm_chip.pio = bus.master
+        self.fake_uart1.pio = bus.master
+        self.fake_uart2.pio = bus.master
+        self.fake_uart3.pio = bus.master
+        self.fake_uart4.pio = bus.master
+        self.fake_ppc.pio = bus.master
+        self.fake_OROM.pio = bus.master
+        self.fake_pnp_addr.pio = bus.master
+        self.fake_pnp_write.pio = bus.master
+        self.fake_pnp_read0.pio = bus.master
+        self.fake_pnp_read1.pio = bus.master
+        self.fake_pnp_read2.pio = bus.master
+        self.fake_pnp_read3.pio = bus.master
+        self.fake_pnp_read4.pio = bus.master
+        self.fake_pnp_read5.pio = bus.master
+        self.fake_pnp_read6.pio = bus.master
+        self.fake_pnp_read7.pio = bus.master
+        self.fake_ata0.pio = bus.master
+        self.fake_ata1.pio = bus.master
+        self.fb.pio = bus.master
+        self.io.pio = bus.master
+        self.uart.pio = bus.master
+        self.backdoor.pio = bus.master
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 3da47399e..e42bc4b94 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -181,10 +181,10 @@ class RealViewPBX(RealView):
     # Attach I/O devices that are on chip and also set the appropriate
     # ranges for the bridge
     def attachOnChipIO(self, bus, bridge):
-       self.gic.pio = bus.port
-       self.l2x0_fake.pio = bus.port
-       self.a9scu.pio = bus.port
-       self.local_cpu_timer.pio = bus.port
+       self.gic.pio = bus.master
+       self.l2x0_fake.pio = bus.master
+       self.a9scu.pio = bus.master
+       self.local_cpu_timer.pio = bus.master
        # Bridge ranges based on excluding what is part of on-chip I/O
        # (gic, l2x0, a9scu, local_cpu_timer)
        bridge.ranges = [AddrRange(self.realview_io.pio_addr,
@@ -195,33 +195,33 @@ class RealViewPBX(RealView):
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-       self.uart.pio          = bus.port
-       self.realview_io.pio   = bus.port
-       self.timer0.pio        = bus.port
-       self.timer1.pio        = bus.port
-       self.clcd.pio          = bus.port
-       self.clcd.dma          = bus.port
-       self.kmi0.pio          = bus.port
-       self.kmi1.pio          = bus.port
-       self.cf_ctrl.pio       = bus.port
-       self.cf_ctrl.config    = bus.port
-       self.cf_ctrl.dma       = bus.port
-       self.dmac_fake.pio     = bus.port
-       self.uart1_fake.pio    = bus.port
-       self.uart2_fake.pio    = bus.port
-       self.uart3_fake.pio    = bus.port
-       self.smc_fake.pio      = bus.port
-       self.sp810_fake.pio    = bus.port
-       self.watchdog_fake.pio = bus.port
-       self.gpio0_fake.pio    = bus.port
-       self.gpio1_fake.pio    = bus.port
-       self.gpio2_fake.pio    = bus.port
-       self.ssp_fake.pio      = bus.port
-       self.sci_fake.pio      = bus.port
-       self.aaci_fake.pio     = bus.port
-       self.mmc_fake.pio      = bus.port
-       self.rtc_fake.pio      = bus.port
-       self.flash_fake.pio    = bus.port
+       self.uart.pio          = bus.master
+       self.realview_io.pio   = bus.master
+       self.timer0.pio        = bus.master
+       self.timer1.pio        = bus.master
+       self.clcd.pio          = bus.master
+       self.clcd.dma          = bus.slave
+       self.kmi0.pio          = bus.master
+       self.kmi1.pio          = bus.master
+       self.cf_ctrl.pio       = bus.master
+       self.cf_ctrl.config    = bus.master
+       self.cf_ctrl.dma       = bus.slave
+       self.dmac_fake.pio     = bus.master
+       self.uart1_fake.pio    = bus.master
+       self.uart2_fake.pio    = bus.master
+       self.uart3_fake.pio    = bus.master
+       self.smc_fake.pio      = bus.master
+       self.sp810_fake.pio    = bus.master
+       self.watchdog_fake.pio = bus.master
+       self.gpio0_fake.pio    = bus.master
+       self.gpio1_fake.pio    = bus.master
+       self.gpio2_fake.pio    = bus.master
+       self.ssp_fake.pio      = bus.master
+       self.sci_fake.pio      = bus.master
+       self.aaci_fake.pio     = bus.master
+       self.mmc_fake.pio      = bus.master
+       self.rtc_fake.pio      = bus.master
+       self.flash_fake.pio    = bus.master
 
 # Reference for memory map and interrupt number
 # RealView Emulation Baseboard User Guide (ARM DUI 0143B)
@@ -261,8 +261,8 @@ class RealViewEB(RealView):
     # Attach I/O devices that are on chip and also set the appropriate
     # ranges for the bridge
     def attachOnChipIO(self, bus, bridge):
-       self.gic.pio = bus.port
-       self.l2x0_fake.pio = bus.port
+       self.gic.pio = bus.master
+       self.l2x0_fake.pio = bus.master
        # Bridge ranges based on excluding what is part of on-chip I/O
        # (gic, l2x0)
        bridge.ranges = [AddrRange(self.realview_io.pio_addr,
@@ -273,31 +273,31 @@ class RealViewEB(RealView):
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-       self.uart.pio          = bus.port
-       self.realview_io.pio   = bus.port
-       self.timer0.pio        = bus.port
-       self.timer1.pio        = bus.port
-       self.clcd.pio          = bus.port
-       self.clcd.dma          = bus.port
-       self.kmi0.pio          = bus.port
-       self.kmi1.pio          = bus.port
-       self.dmac_fake.pio     = bus.port
-       self.uart1_fake.pio    = bus.port
-       self.uart2_fake.pio    = bus.port
-       self.uart3_fake.pio    = bus.port
-       self.smc_fake.pio      = bus.port
-       self.sp810_fake.pio    = bus.port
-       self.watchdog_fake.pio = bus.port
-       self.gpio0_fake.pio    = bus.port
-       self.gpio1_fake.pio    = bus.port
-       self.gpio2_fake.pio    = bus.port
-       self.ssp_fake.pio      = bus.port
-       self.sci_fake.pio      = bus.port
-       self.aaci_fake.pio     = bus.port
-       self.mmc_fake.pio      = bus.port
-       self.rtc_fake.pio      = bus.port
-       self.flash_fake.pio    = bus.port
-       self.smcreg_fake.pio   = bus.port
+       self.uart.pio          = bus.master
+       self.realview_io.pio   = bus.master
+       self.timer0.pio        = bus.master
+       self.timer1.pio        = bus.master
+       self.clcd.pio          = bus.master
+       self.clcd.dma          = bus.slave
+       self.kmi0.pio          = bus.master
+       self.kmi1.pio          = bus.master
+       self.dmac_fake.pio     = bus.master
+       self.uart1_fake.pio    = bus.master
+       self.uart2_fake.pio    = bus.master
+       self.uart3_fake.pio    = bus.master
+       self.smc_fake.pio      = bus.master
+       self.sp810_fake.pio    = bus.master
+       self.watchdog_fake.pio = bus.master
+       self.gpio0_fake.pio    = bus.master
+       self.gpio1_fake.pio    = bus.master
+       self.gpio2_fake.pio    = bus.master
+       self.ssp_fake.pio      = bus.master
+       self.sci_fake.pio      = bus.master
+       self.aaci_fake.pio     = bus.master
+       self.mmc_fake.pio      = bus.master
+       self.rtc_fake.pio      = bus.master
+       self.flash_fake.pio    = bus.master
+       self.smcreg_fake.pio   = bus.master
 
 class VExpress_ELT(RealView):
     pci_cfg_base = 0xD0000000
@@ -349,9 +349,9 @@ class VExpress_ELT(RealView):
     # Attach I/O devices that are on chip and also set the appropriate
     # ranges for the bridge
     def attachOnChipIO(self, bus, bridge):
-       self.gic.pio = bus.port
-       self.a9scu.pio = bus.port
-       self.local_cpu_timer.pio = bus.port
+       self.gic.pio = bus.master
+       self.a9scu.pio = bus.master
+       self.local_cpu_timer.pio = bus.master
        # Bridge ranges based on excluding what is part of on-chip I/O
        # (gic, a9scu)
        bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
@@ -361,44 +361,44 @@ class VExpress_ELT(RealView):
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-       self.elba_uart.pio       = bus.port
-       self.uart.pio            = bus.port
-       self.realview_io.pio     = bus.port
-       self.v2m_timer0.pio      = bus.port
-       self.v2m_timer1.pio      = bus.port
-       self.elba_timer0.pio     = bus.port
-       self.elba_timer1.pio     = bus.port
-       self.clcd.pio            = bus.port
-       self.clcd.dma            = bus.port
-       self.kmi0.pio            = bus.port
-       self.kmi1.pio            = bus.port
-       self.elba_kmi0.pio       = bus.port
-       self.elba_kmi1.pio       = bus.port
-       self.cf_ctrl.pio         = bus.port
-       self.cf_ctrl.config      = bus.port
+       self.elba_uart.pio       = bus.master
+       self.uart.pio            = bus.master
+       self.realview_io.pio     = bus.master
+       self.v2m_timer0.pio      = bus.master
+       self.v2m_timer1.pio      = bus.master
+       self.elba_timer0.pio     = bus.master
+       self.elba_timer1.pio     = bus.master
+       self.clcd.pio            = bus.master
+       self.clcd.dma            = bus.slave
+       self.kmi0.pio            = bus.master
+       self.kmi1.pio            = bus.master
+       self.elba_kmi0.pio       = bus.master
+       self.elba_kmi1.pio       = bus.master
+       self.cf_ctrl.pio         = bus.master
+       self.cf_ctrl.config      = bus.master
        self.cf_ctrl.dma         = bus.port
-       self.ide.pio             = bus.port
-       self.ide.config          = bus.port
-       self.ide.dma             = bus.port
-       self.ethernet.pio        = bus.port
-       self.ethernet.config     = bus.port
-       self.ethernet.dma        = bus.port
+       self.ide.pio             = bus.master
+       self.ide.config          = bus.master
+       self.ide.dma             = bus.slave
+       self.ethernet.pio        = bus.master
+       self.ethernet.config     = bus.master
+       self.ethernet.dma        = bus.slave
        self.pciconfig.pio       = bus.default
        bus.use_default_range    = True
 
-       self.l2x0_fake.pio       = bus.port
-       self.dmac_fake.pio       = bus.port
-       self.uart1_fake.pio      = bus.port
-       self.uart2_fake.pio      = bus.port
-       self.uart3_fake.pio      = bus.port
-       self.smc_fake.pio        = bus.port
-       self.sp810_fake.pio      = bus.port
-       self.watchdog_fake.pio   = bus.port
-       self.aaci_fake.pio       = bus.port
-       self.elba_aaci_fake.pio  = bus.port
-       self.mmc_fake.pio        = bus.port
-       self.rtc_fake.pio        = bus.port
-       self.spsc_fake.pio       = bus.port
-       self.lan_fake.pio        = bus.port
-       self.usb_fake.pio        = bus.port
+       self.l2x0_fake.pio       = bus.master
+       self.dmac_fake.pio       = bus.master
+       self.uart1_fake.pio      = bus.master
+       self.uart2_fake.pio      = bus.master
+       self.uart3_fake.pio      = bus.master
+       self.smc_fake.pio        = bus.master
+       self.sp810_fake.pio      = bus.master
+       self.watchdog_fake.pio   = bus.master
+       self.aaci_fake.pio       = bus.master
+       self.elba_aaci_fake.pio  = bus.master
+       self.mmc_fake.pio        = bus.master
+       self.rtc_fake.pio        = bus.master
+       self.spsc_fake.pio       = bus.master
+       self.lan_fake.pio        = bus.master
+       self.usb_fake.pio        = bus.master
 
diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
index d4ab2cb17..09923f6c2 100644
--- a/src/dev/x86/I82094AA.py
+++ b/src/dev/x86/I82094AA.py
@@ -37,7 +37,7 @@ class I82094AA(BasicPioDevice):
     apic_id = Param.Int(1, 'APIC id for this IO APIC')
     pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
     pio_addr = Param.Addr("Device address")
-    int_port = Port("Port for sending and receiving interrupt messages")
+    int_master = MasterPort("Port for sending interrupt messages")
     int_latency = Param.Latency('1ns', \
             "Latency for an interrupt to propagate through this device.")
     external_int_pic = Param.I8259(NULL, "External PIC, if any")
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index bb8c91ac6..5b7d0864e 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -71,12 +71,12 @@ class Pc(Platform):
 
     def attachIO(self, bus):
         self.south_bridge.attachIO(bus)
-        self.i_dont_exist.pio = bus.port
-        self.behind_pci.pio = bus.port
-        self.com_1.pio = bus.port
-        self.fake_com_2.pio = bus.port
-        self.fake_com_3.pio = bus.port
-        self.fake_com_4.pio = bus.port
-        self.fake_floppy.pio = bus.port
+        self.i_dont_exist.pio = bus.master
+        self.behind_pci.pio = bus.master
+        self.com_1.pio = bus.master
+        self.fake_com_2.pio = bus.master
+        self.fake_com_3.pio = bus.master
+        self.fake_com_4.pio = bus.master
+        self.fake_floppy.pio = bus.master
         self.pciconfig.pio = bus.default
         bus.use_default_range = True
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index baff35e0b..9f7070e96 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -102,15 +102,15 @@ class SouthBridge(SimObject):
         self.speaker.i8254 = self.pit
         self.io_apic.external_int_pic = self.pic1
         # Connect to the bus
-        self.cmos.pio = bus.port
-        self.dma1.pio = bus.port
-        self.ide.pio = bus.port
-        self.ide.config = bus.port
-        self.ide.dma = bus.port
-        self.keyboard.pio = bus.port
-        self.pic1.pio = bus.port
-        self.pic2.pio = bus.port
-        self.pit.pio = bus.port
-        self.speaker.pio = bus.port
-        self.io_apic.pio = bus.port
-        self.io_apic.int_port = bus.port
+        self.cmos.pio = bus.master
+        self.dma1.pio = bus.master
+        self.ide.pio = bus.master
+        self.ide.config = bus.master
+        self.ide.dma = bus.slave
+        self.keyboard.pio = bus.master
+        self.pic1.pio = bus.master
+        self.pic2.pio = bus.master
+        self.pit.pio = bus.master
+        self.speaker.pio = bus.master
+        self.io_apic.pio = bus.master
+        self.io_apic.int_master = bus.slave
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index dfef059c3..60ef27012 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -123,7 +123,7 @@ class I82094AA : public PioDevice, public IntDev
 
     Port *getPort(const std::string &if_name, int idx = -1)
     {
-        if (if_name == "int_port")
+        if (if_name == "int_master")
             return intPort;
         return PioDevice::getPort(if_name, idx);
     }
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index 9713d042b..05b4d12a1 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -90,7 +90,7 @@ class IntDev
     IntDev(MemObject * parent, Tick latency = 0)
     {
         if (parent != NULL) {
-            intPort = new IntPort(parent->name() + ".int_port",
+            intPort = new IntPort(parent->name() + ".int_master",
                     parent, this, latency);
         } else {
             intPort = NULL;