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authorGabe Black <gblack@eecs.umich.edu>2009-02-01 00:26:10 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-01 00:26:10 -0800
commit70cd5bfce5549495c6e969fa509bfd5f56190e10 (patch)
tree0d5bf42d04a037195dd9ea97b4dfbe3054cdb8d7 /src/dev
parentf1b43b39a764645c8e15b66a1a01d404f03c8307 (diff)
downloadgem5-70cd5bfce5549495c6e969fa509bfd5f56190e10.tar.xz
X86: Configure the first PCI interrupt.
Diffstat (limited to 'src/dev')
-rw-r--r--src/dev/x86/SouthBridge.py3
-rw-r--r--src/dev/x86/pc.cc6
2 files changed, 8 insertions, 1 deletions
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 8d766471e..d89ed9dc6 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -87,7 +87,8 @@ class SouthBridge(SimObject):
ide.BAR3LegacyIO = True
ide.BAR4 = 1
ide.Command = 1
- ide.InterruptLine = 20
+ ide.InterruptLine = 14
+ ide.InterruptPin = 1
def attachIO(self, bus):
# Route interupt signals
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index 5005bd296..d23474c67 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -101,6 +101,12 @@ Pc::init()
entry.vector = 0x2C;
ioApic.writeReg(0x28, entry.bottomDW);
ioApic.writeReg(0x29, entry.topDW);
+ entry.vector = 0x2E;
+ ioApic.writeReg(0x2C, entry.bottomDW);
+ ioApic.writeReg(0x2D, entry.topDW);
+ entry.vector = 0x30;
+ ioApic.writeReg(0x30, entry.bottomDW);
+ ioApic.writeReg(0x31, entry.topDW);
}
Tick