More changes to get SPARC fs closer. Now at 1.2M cycles before difference

configs/common/FSConfig.py:
    seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
    change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
    For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
    Use instruction count from cpu rather than cycles because that is what legion does
    we can change it back after were done with legion
src/base/bitfield.hh:
    add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
    add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
    compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
    change asserts of packet success to if panics wrapped with NDEBUG defines
    so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
    expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
    convert some tabs to spaces
src/python/m5/objects/T1000.py:
    add more fake devices for each l1 bank and each memory controller

--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276

2 files changed, 82 insertions, 10 deletions

diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc
index 40909c6a1..c36ddeb83 100644
--- a/src/dev/isa_fake.cc
+++ b/src/dev/isa_fake.cc
@@ -47,7 +47,10 @@ IsaFake::IsaFake(Params *p)
     if (!params()->retBadAddr)
         pioSize = p->pio_size;
 
-    memset(&retData, p->retData, sizeof(retData));
+    retData8 = params()->retData8;
+    retData16 = params()->retData16;
+    retData32 = params()->retData32;
+    retData64 = params()->retData64;
 }
 
 Tick
@@ -55,6 +58,9 @@ IsaFake::read(PacketPtr pkt)
 {
     assert(pkt->result == Packet::Unknown);
 
+    if (params()->warnAccess != "")
+        warn("Device %s accessed by read to address %#x size=%d\n",
+                name(), pkt->getAddr(), pkt->getSize());
     if (params()->retBadAddr) {
         DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
                 pkt->getAddr(), pkt->getSize());
@@ -65,16 +71,16 @@ IsaFake::read(PacketPtr pkt)
                 pkt->getAddr(), pkt->getSize());
         switch (pkt->getSize()) {
           case sizeof(uint64_t):
-             pkt->set(retData);
+             pkt->set(retData64);
              break;
           case sizeof(uint32_t):
-             pkt->set((uint32_t)retData);
+             pkt->set(retData32);
              break;
           case sizeof(uint16_t):
-             pkt->set((uint16_t)retData);
+             pkt->set(retData16);
              break;
           case sizeof(uint8_t):
-             pkt->set((uint8_t)retData);
+             pkt->set(retData8);
              break;
           default:
             panic("invalid access size!\n");
@@ -87,6 +93,27 @@ IsaFake::read(PacketPtr pkt)
 Tick
 IsaFake::write(PacketPtr pkt)
 {
+    if (params()->warnAccess != "") {
+        uint64_t data;
+        switch (pkt->getSize()) {
+          case sizeof(uint64_t):
+            data = pkt->get<uint64_t>();
+            break;
+          case sizeof(uint32_t):
+            data = pkt->get<uint32_t>();
+            break;
+          case sizeof(uint16_t):
+            data = pkt->get<uint16_t>();
+            break;
+          case sizeof(uint8_t):
+            data = pkt->get<uint8_t>();
+            break;
+          default:
+            panic("invalid access size!\n");
+        }
+        warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
+                name(), pkt->getAddr(), pkt->getSize(), data);
+    }
     if (params()->retBadAddr) {
         DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
                 pkt->getAddr(), pkt->getSize());
@@ -94,6 +121,25 @@ IsaFake::write(PacketPtr pkt)
     } else {
         DPRINTF(Tsunami, "write - va=%#x size=%d \n",
                 pkt->getAddr(), pkt->getSize());
+
+        if (params()->updateData) {
+            switch (pkt->getSize()) {
+              case sizeof(uint64_t):
+                retData64 = pkt->get<uint64_t>();
+                break;
+              case sizeof(uint32_t):
+                retData32 = pkt->get<uint32_t>();
+                break;
+              case sizeof(uint16_t):
+                retData16 = pkt->get<uint16_t>();
+                break;
+              case sizeof(uint8_t):
+                retData8 = pkt->get<uint8_t>();
+                break;
+              default:
+                panic("invalid access size!\n");
+            }
+        }
         pkt->result = Packet::Success;
     }
     return pioDelay;
@@ -105,7 +151,12 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
     Param<Tick> pio_latency;
     Param<Addr> pio_size;
     Param<bool> ret_bad_addr;
-    Param<uint8_t> ret_data;
+    Param<bool> update_data;
+    Param<std::string> warn_access;
+    Param<uint8_t> ret_data8;
+    Param<uint16_t> ret_data16;
+    Param<uint32_t> ret_data32;
+    Param<uint64_t> ret_data64;
     SimObjectParam<Platform *> platform;
     SimObjectParam<System *> system;
 
@@ -117,7 +168,12 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
     INIT_PARAM(pio_latency, "Programmed IO latency"),
     INIT_PARAM(pio_size, "Size of address range"),
     INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"),
-    INIT_PARAM(ret_data, "Data to return if not bad addr"),
+    INIT_PARAM(update_data, "Update returned data"),
+    INIT_PARAM(warn_access, "Warn if this device is touched"),
+    INIT_PARAM(ret_data8, "Data to return if not bad addr"),
+    INIT_PARAM(ret_data16, "Data to return if not bad addr"),
+    INIT_PARAM(ret_data32, "Data to return if not bad addr"),
+    INIT_PARAM(ret_data64, "Data to return if not bad addr"),
     INIT_PARAM(platform, "platform"),
     INIT_PARAM(system, "system object")
 
@@ -131,7 +187,12 @@ CREATE_SIM_OBJECT(IsaFake)
     p->pio_delay = pio_latency;
     p->pio_size = pio_size;
     p->retBadAddr = ret_bad_addr;
-    p->retData = ret_data;
+    p->updateData = update_data;
+    p->warnAccess = warn_access;
+    p->retData8= ret_data8;
+    p->retData16 = ret_data16;
+    p->retData32 = ret_data32;
+    p->retData64 = ret_data64;
     p->platform = platform;
     p->system = system;
     return new IsaFake(p);
diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh
index fee41e325..dc2ad48e8 100644
--- a/src/dev/isa_fake.hh
+++ b/src/dev/isa_fake.hh
@@ -40,6 +40,8 @@
 #include "dev/alpha/tsunami.hh"
 #include "mem/packet.hh"
 
+#include <string>
+
 /**
  * IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
  *  rites. It is meant to be placed at an address range
@@ -54,11 +56,20 @@ class IsaFake : public BasicPioDevice
     {
         Addr pio_size;
         bool retBadAddr;
-        uint8_t retData;
+        bool updateData;
+        uint8_t retData8;
+        uint16_t retData16;
+        uint32_t retData32;
+        uint64_t retData64;
+        std::string warnAccess;
     };
   protected:
     const Params *params() const { return (const Params*)_params; }
-    uint64_t retData;
+    uint8_t retData8;
+    uint16_t retData16;
+    uint32_t retData32;
+    uint64_t retData64;
+
 
   public:
     /**