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authorSteve Reinhardt <stever@gmail.com>2013-07-11 21:56:24 -0500
committerSteve Reinhardt <stever@gmail.com>2013-07-11 21:56:24 -0500
commitb0b1c0205c438d382aaec54ee4b79b92e1a5e285 (patch)
treef490b704b90dfaba13254565a8d59770b9cddbed /src/dev
parent8e54c93222cd69dd4c388adc37cded7b7eebef76 (diff)
downloadgem5-b0b1c0205c438d382aaec54ee4b79b92e1a5e285.tar.xz
devices: make more classes derive from BasicPioDevice
A couple of devices that have single fixed memory mapped regions were not derived from BasicPioDevice, when that's exactly the functionality that BasicPioDevice provides. This patch gets rid of a little bit of redundant code by making those devices actually do so. Also fixed the weird case of X86ISA::Interrupts, where the class already did derive from BasicPioDevice but didn't actually use all the features it could have. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/dev')
-rw-r--r--src/dev/Pci.py6
-rw-r--r--src/dev/pciconfigall.cc19
-rw-r--r--src/dev/pciconfigall.hh8
-rw-r--r--src/dev/x86/i82094aa.cc33
-rw-r--r--src/dev/x86/i82094aa.hh29
5 files changed, 41 insertions, 54 deletions
diff --git a/src/dev/Pci.py b/src/dev/Pci.py
index df7c773c4..a63c329a4 100644
--- a/src/dev/Pci.py
+++ b/src/dev/Pci.py
@@ -31,14 +31,16 @@ from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice, DmaDevice, PioDevice
-class PciConfigAll(PioDevice):
+class PciConfigAll(BasicPioDevice):
type = 'PciConfigAll'
cxx_header = "dev/pciconfigall.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of.")
- pio_latency = Param.Latency('30ns', "Programmed IO latency")
bus = Param.UInt8(0x00, "PCI bus to act as config space for")
size = Param.MemorySize32('16MB', "Size of config space")
+ pio_latency = '30ns'
+ pio_addr = 0 # will be overridden by platform-based calculation
+
class PciDevice(DmaDevice):
type = 'PciDevice'
diff --git a/src/dev/pciconfigall.cc b/src/dev/pciconfigall.cc
index 4fe3b4641..d5ebb7d57 100644
--- a/src/dev/pciconfigall.cc
+++ b/src/dev/pciconfigall.cc
@@ -44,9 +44,13 @@
#include "sim/system.hh"
PciConfigAll::PciConfigAll(const Params *p)
- : PioDevice(p)
+ : BasicPioDevice(p)
{
+ // the pio_addr Python parameter is ignored, and overridden by
+ // this caluclated value
pioAddr = p->platform->calcPciConfigAddr(params()->bus,0,0);
+
+ pioSize = params()->size;
}
@@ -73,26 +77,17 @@ PciConfigAll::read(PacketPtr pkt)
panic("invalid access size(?) for PCI configspace!\n");
}
pkt->makeAtomicResponse();
- return params()->pio_latency;
+ return pioDelay;
}
Tick
PciConfigAll::write(PacketPtr pkt)
{
- panic("Attempting to write to config space on non-existant device\n");
+ panic("Attempting to write to config space on non-existent device\n");
M5_DUMMY_RETURN
}
-AddrRangeList
-PciConfigAll::getAddrRanges() const
-{
- AddrRangeList ranges;
- ranges.push_back(RangeSize(pioAddr, params()->size));
- return ranges;
-}
-
-
#ifndef DOXYGEN_SHOULD_SKIP_THIS
PciConfigAll *
diff --git a/src/dev/pciconfigall.hh b/src/dev/pciconfigall.hh
index 4df36f0b3..615b3578f 100644
--- a/src/dev/pciconfigall.hh
+++ b/src/dev/pciconfigall.hh
@@ -48,7 +48,7 @@
* space and passes the requests on to TsunamiPCIDev devices as
* appropriate.
*/
-class PciConfigAll : public PioDevice
+class PciConfigAll : public BasicPioDevice
{
public:
typedef PciConfigAllParams Params;
@@ -78,12 +78,6 @@ class PciConfigAll : public PioDevice
*/
virtual Tick write(PacketPtr pkt);
-
- AddrRangeList getAddrRanges() const;
-
- private:
- Addr pioAddr;
-
};
#endif // __PCICONFIGALL_HH__
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index 0692718bf..1d3defa12 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -38,10 +38,9 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
-X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p),
- IntDev(this, p->int_latency),
- latency(p->pio_latency), pioAddr(p->pio_addr),
- extIntPic(p->external_int_pic), lowestPriorityOffset(0)
+X86ISA::I82094AA::I82094AA(Params *p)
+ : BasicPioDevice(p), IntDev(this, p->int_latency),
+ extIntPic(p->external_int_pic), lowestPriorityOffset(0)
{
// This assumes there's only one I/O APIC in the system and since the apic
// id is stored in a 8-bit field with 0xff meaning broadcast, the id must
@@ -57,6 +56,8 @@ X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p),
redirTable[i] = entry;
pinStates[i] = false;
}
+
+ pioSize = 20;
}
void
@@ -66,10 +67,28 @@ X86ISA::I82094AA::init()
// via the piodevice init() function and its int port that it inherited
// from IntDev. Note IntDev is not a SimObject itself.
- PioDevice::init();
+ BasicPioDevice::init();
IntDev::init();
}
+BaseMasterPort &
+X86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx)
+{
+ if (if_name == "int_master")
+ return intMasterPort;
+ return BasicPioDevice::getMasterPort(if_name, idx);
+}
+
+AddrRangeList
+X86ISA::I82094AA::getIntAddrRange() const
+{
+ AddrRangeList ranges;
+ ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
+ x86InterruptAddress(initialApicId, 0) +
+ PhysAddrAPICRangeSize));
+ return ranges;
+}
+
Tick
X86ISA::I82094AA::read(PacketPtr pkt)
{
@@ -86,7 +105,7 @@ X86ISA::I82094AA::read(PacketPtr pkt)
panic("Illegal read from I/O APIC.\n");
}
pkt->makeAtomicResponse();
- return latency;
+ return pioDelay;
}
Tick
@@ -105,7 +124,7 @@ X86ISA::I82094AA::write(PacketPtr pkt)
panic("Illegal write to I/O APIC.\n");
}
pkt->makeAtomicResponse();
- return latency;
+ return pioDelay;
}
void
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index f5e292baa..a8d79fde1 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -44,7 +44,7 @@ namespace X86ISA
class I8259;
class Interrupts;
-class I82094AA : public PioDevice, public IntDev
+class I82094AA : public BasicPioDevice, public IntDev
{
public:
BitUnion64(RedirTableEntry)
@@ -64,9 +64,6 @@ class I82094AA : public PioDevice, public IntDev
EndBitUnion(RedirTableEntry)
protected:
- Tick latency;
- Addr pioAddr;
-
I8259 * extIntPic;
uint8_t regSel;
@@ -100,33 +97,13 @@ class I82094AA : public PioDevice, public IntDev
Tick read(PacketPtr pkt);
Tick write(PacketPtr pkt);
- AddrRangeList getAddrRanges() const
- {
- AddrRangeList ranges;
- ranges.push_back(RangeEx(pioAddr, pioAddr + 4));
- ranges.push_back(RangeEx(pioAddr + 16, pioAddr + 20));
- return ranges;
- }
-
- AddrRangeList getIntAddrRange() const
- {
- AddrRangeList ranges;
- ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
- x86InterruptAddress(initialApicId, 0) +
- PhysAddrAPICRangeSize));
- return ranges;
- }
+ AddrRangeList getIntAddrRange() const;
void writeReg(uint8_t offset, uint32_t value);
uint32_t readReg(uint8_t offset);
BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID)
- {
- if (if_name == "int_master")
- return intMasterPort;
- return PioDevice::getMasterPort(if_name, idx);
- }
+ PortID idx = InvalidPortID);
void signalInterrupt(int line);
void raiseInterruptPin(int number);