Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
    Change ExecContext to ThreadContext.

--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e

4 files changed, 10 insertions, 10 deletions

diff --git a/src/dev/alpha_console.cc b/src/dev/alpha_console.cc
index aa3261f01..181bbf934 100644
--- a/src/dev/alpha_console.cc
+++ b/src/dev/alpha_console.cc
@@ -43,7 +43,7 @@
 #include "base/str.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "dev/alpha_console.hh"
 #include "dev/platform.hh"
 #include "dev/simconsole.hh"
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index 1f2fea418..decffaf73 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -37,7 +37,7 @@
 
 #include "arch/alpha/ev5.hh"
 #include "base/inet.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "dev/etherlink.hh"
 #include "dev/ns_gige.hh"
 #include "dev/pciconfigall.hh"
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index d186c0036..a0223733b 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -33,7 +33,7 @@
 #include <string>
 
 #include "base/inet.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/intr_control.hh"
 #include "dev/etherlink.hh"
 #include "dev/sinic.hh"
diff --git a/src/dev/tsunami_cchip.cc b/src/dev/tsunami_cchip.cc
index e4be98642..3feb7439f 100644
--- a/src/dev/tsunami_cchip.cc
+++ b/src/dev/tsunami_cchip.cc
@@ -43,7 +43,7 @@
 #include "dev/tsunamireg.h"
 #include "dev/tsunami.hh"
 #include "mem/port.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/intr_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
@@ -368,7 +368,7 @@ TsunamiCChip::write(Packet *pkt)
 void
 TsunamiCChip::clearIPI(uint64_t ipintr)
 {
-    int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+    int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
     assert(numcpus <= Tsunami::Max_CPUs);
 
     if (ipintr) {
@@ -394,7 +394,7 @@ TsunamiCChip::clearIPI(uint64_t ipintr)
 void
 TsunamiCChip::clearITI(uint64_t itintr)
 {
-    int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+    int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
     assert(numcpus <= Tsunami::Max_CPUs);
 
     if (itintr) {
@@ -414,7 +414,7 @@ TsunamiCChip::clearITI(uint64_t itintr)
 void
 TsunamiCChip::reqIPI(uint64_t ipreq)
 {
-    int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+    int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
     assert(numcpus <= Tsunami::Max_CPUs);
 
     if (ipreq) {
@@ -441,7 +441,7 @@ TsunamiCChip::reqIPI(uint64_t ipreq)
 void
 TsunamiCChip::postRTC()
 {
-    int size = tsunami->intrctrl->cpu->system->execContexts.size();
+    int size = tsunami->intrctrl->cpu->system->threadContexts.size();
     assert(size <= Tsunami::Max_CPUs);
 
     for (int i = 0; i < size; i++) {
@@ -459,7 +459,7 @@ void
 TsunamiCChip::postDRIR(uint32_t interrupt)
 {
     uint64_t bitvector = ULL(1) << interrupt;
-    uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+    uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
     assert(size <= Tsunami::Max_CPUs);
     drir |= bitvector;
 
@@ -477,7 +477,7 @@ void
 TsunamiCChip::clearDRIR(uint32_t interrupt)
 {
     uint64_t bitvector = ULL(1) << interrupt;
-    uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+    uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
     assert(size <= Tsunami::Max_CPUs);
 
     if (drir & bitvector)