gcc: Clean-up of non-C++0x compliant code, first steps

This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).

3 files changed, 98 insertions, 98 deletions

diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh
index 1e50be165..7c31222ed 100644
--- a/src/dev/i8254xGBe.hh
+++ b/src/dev/i8254xGBe.hh
@@ -430,7 +430,7 @@ class IGbE : public EtherDevice
         Addr tsoMss;
         Addr tsoTotalLen;
         Addr tsoUsedLen;
-        Addr tsoPrevSeq;;
+        Addr tsoPrevSeq;
         Addr tsoPktPayloadBytes;
         bool tsoLoadedHeader;
         bool tsoPktHasHeader;
diff --git a/src/dev/ide_atareg.h b/src/dev/ide_atareg.h
index b9f1d9e0f..d19a75462 100644
--- a/src/dev/ide_atareg.h
+++ b/src/dev/ide_atareg.h
@@ -33,7 +33,7 @@
 #ifndef _DEV_ATA_ATAREG_H_
 #define _DEV_ATA_ATAREG_H_
 
-#if defined(linux)
+#if defined(__linux__)
 #include <endian.h>
 #elif defined(__sun)
 #include <sys/isa_defs.h>
diff --git a/src/dev/sinicreg.hh b/src/dev/sinicreg.hh
index 43dc46dc4..540e690b0 100644
--- a/src/dev/sinicreg.hh
+++ b/src/dev/sinicreg.hh
@@ -31,8 +31,8 @@
 #ifndef __DEV_SINICREG_HH__
 #define __DEV_SINICREG_HH__
 
-#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL)
-#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL)
+#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL);
+#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL);
 
 #define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
         static const uint32_t NAME##_width = WIDTH; \
@@ -61,114 +61,114 @@ static const int VirtualShift = 8;
 static const int VirtualMask = 0xff;
 
 // Registers
-__SINIC_REG32(Config,        0x00); // 32: configuration register
-__SINIC_REG32(Command,       0x04); // 32: command register
-__SINIC_REG32(IntrStatus,    0x08); // 32: interrupt status
-__SINIC_REG32(IntrMask,      0x0c); // 32: interrupt mask
-__SINIC_REG32(RxMaxCopy,     0x10); // 32: max bytes per rx copy
-__SINIC_REG32(TxMaxCopy,     0x14); // 32: max bytes per tx copy
-__SINIC_REG32(ZeroCopySize,  0x18); // 32: bytes to copy if below threshold
-__SINIC_REG32(ZeroCopyMark,  0x1c); // 32: only zero-copy above this threshold
-__SINIC_REG32(VirtualCount,  0x20); // 32: number of virutal NICs
-__SINIC_REG32(RxMaxIntr,     0x24); // 32: max receives per interrupt
-__SINIC_REG32(RxFifoSize,    0x28); // 32: rx fifo capacity in bytes
-__SINIC_REG32(TxFifoSize,    0x2c); // 32: tx fifo capacity in bytes
-__SINIC_REG32(RxFifoLow,     0x30); // 32: rx fifo low watermark
-__SINIC_REG32(TxFifoLow,     0x34); // 32: tx fifo low watermark
-__SINIC_REG32(RxFifoHigh,    0x38); // 32: rx fifo high watermark
-__SINIC_REG32(TxFifoHigh,    0x3c); // 32: tx fifo high watermark
-__SINIC_REG32(RxData,        0x40); // 64: receive data
-__SINIC_REG32(RxDone,        0x48); // 64: receive done
-__SINIC_REG32(RxWait,        0x50); // 64: receive done (busy wait)
-__SINIC_REG32(TxData,        0x58); // 64: transmit data
-__SINIC_REG32(TxDone,        0x60); // 64: transmit done
-__SINIC_REG32(TxWait,        0x68); // 64: transmit done (busy wait)
-__SINIC_REG32(HwAddr,        0x70); // 64: mac address
-__SINIC_REG32(RxStatus,      0x78);
-__SINIC_REG32(Size,          0x80); // register addres space size
+__SINIC_REG32(Config,        0x00) // 32: configuration register
+__SINIC_REG32(Command,       0x04) // 32: command register
+__SINIC_REG32(IntrStatus,    0x08) // 32: interrupt status
+__SINIC_REG32(IntrMask,      0x0c) // 32: interrupt mask
+__SINIC_REG32(RxMaxCopy,     0x10) // 32: max bytes per rx copy
+__SINIC_REG32(TxMaxCopy,     0x14) // 32: max bytes per tx copy
+__SINIC_REG32(ZeroCopySize,  0x18) // 32: bytes to copy if below threshold
+__SINIC_REG32(ZeroCopyMark,  0x1c) // 32: only zero-copy above this threshold
+__SINIC_REG32(VirtualCount,  0x20) // 32: number of virutal NICs
+__SINIC_REG32(RxMaxIntr,     0x24) // 32: max receives per interrupt
+__SINIC_REG32(RxFifoSize,    0x28) // 32: rx fifo capacity in bytes
+__SINIC_REG32(TxFifoSize,    0x2c) // 32: tx fifo capacity in bytes
+__SINIC_REG32(RxFifoLow,     0x30) // 32: rx fifo low watermark
+__SINIC_REG32(TxFifoLow,     0x34) // 32: tx fifo low watermark
+__SINIC_REG32(RxFifoHigh,    0x38) // 32: rx fifo high watermark
+__SINIC_REG32(TxFifoHigh,    0x3c) // 32: tx fifo high watermark
+__SINIC_REG32(RxData,        0x40) // 64: receive data
+__SINIC_REG32(RxDone,        0x48) // 64: receive done
+__SINIC_REG32(RxWait,        0x50) // 64: receive done (busy wait)
+__SINIC_REG32(TxData,        0x58) // 64: transmit data
+__SINIC_REG32(TxDone,        0x60) // 64: transmit done
+__SINIC_REG32(TxWait,        0x68) // 64: transmit done (busy wait)
+__SINIC_REG32(HwAddr,        0x70) // 64: mac address
+__SINIC_REG32(RxStatus,      0x78)
+__SINIC_REG32(Size,          0x80) // register addres space size
 
 // Config register bits
-__SINIC_VAL32(Config_ZeroCopy, 12, 1); // enable zero copy
-__SINIC_VAL32(Config_DelayCopy,11, 1); // enable delayed copy
-__SINIC_VAL32(Config_RSS,      10, 1); // enable receive side scaling
-__SINIC_VAL32(Config_RxThread,  9, 1); // enable receive threads
-__SINIC_VAL32(Config_TxThread,  8, 1); // enable transmit thread
-__SINIC_VAL32(Config_Filter,    7, 1); // enable receive filter
-__SINIC_VAL32(Config_Vlan,      6, 1); // enable vlan tagging
-__SINIC_VAL32(Config_Vaddr,     5, 1); // enable virtual addressing
-__SINIC_VAL32(Config_Desc,      4, 1); // enable tx/rx descriptors
-__SINIC_VAL32(Config_Poll,      3, 1); // enable polling
-__SINIC_VAL32(Config_IntEn,     2, 1); // enable interrupts
-__SINIC_VAL32(Config_TxEn,      1, 1); // enable transmit
-__SINIC_VAL32(Config_RxEn,      0, 1); // enable receive
+__SINIC_VAL32(Config_ZeroCopy, 12, 1) // enable zero copy
+__SINIC_VAL32(Config_DelayCopy,11, 1) // enable delayed copy
+__SINIC_VAL32(Config_RSS,      10, 1) // enable receive side scaling
+__SINIC_VAL32(Config_RxThread,  9, 1) // enable receive threads
+__SINIC_VAL32(Config_TxThread,  8, 1) // enable transmit thread
+__SINIC_VAL32(Config_Filter,    7, 1) // enable receive filter
+__SINIC_VAL32(Config_Vlan,      6, 1) // enable vlan tagging
+__SINIC_VAL32(Config_Vaddr,     5, 1) // enable virtual addressing
+__SINIC_VAL32(Config_Desc,      4, 1) // enable tx/rx descriptors
+__SINIC_VAL32(Config_Poll,      3, 1) // enable polling
+__SINIC_VAL32(Config_IntEn,     2, 1) // enable interrupts
+__SINIC_VAL32(Config_TxEn,      1, 1) // enable transmit
+__SINIC_VAL32(Config_RxEn,      0, 1) // enable receive
 
 // Command register bits
-__SINIC_VAL32(Command_Intr,  1, 1); // software interrupt
-__SINIC_VAL32(Command_Reset, 0, 1); // reset chip
+__SINIC_VAL32(Command_Intr,  1, 1) // software interrupt
+__SINIC_VAL32(Command_Reset, 0, 1) // reset chip
 
 // Interrupt register bits
-__SINIC_VAL32(Intr_Soft,      8, 1); // software interrupt
-__SINIC_VAL32(Intr_TxLow,     7, 1); // tx fifo dropped below watermark
-__SINIC_VAL32(Intr_TxFull,    6, 1); // tx fifo full
-__SINIC_VAL32(Intr_TxDMA,     5, 1); // tx dma completed w/ interrupt
-__SINIC_VAL32(Intr_TxPacket,  4, 1); // packet transmitted
-__SINIC_VAL32(Intr_RxHigh,    3, 1); // rx fifo above high watermark
-__SINIC_VAL32(Intr_RxEmpty,   2, 1); // rx fifo empty
-__SINIC_VAL32(Intr_RxDMA,     1, 1); // rx dma completed w/ interrupt
-__SINIC_VAL32(Intr_RxPacket,  0, 1); // packet received
-__SINIC_REG32(Intr_All,       0x01ff); // all valid interrupts
-__SINIC_REG32(Intr_NoDelay,   0x01cc); // interrupts that aren't coalesced
-__SINIC_REG32(Intr_Res,      ~0x01ff); // reserved interrupt bits
+__SINIC_VAL32(Intr_Soft,      8, 1) // software interrupt
+__SINIC_VAL32(Intr_TxLow,     7, 1) // tx fifo dropped below watermark
+__SINIC_VAL32(Intr_TxFull,    6, 1) // tx fifo full
+__SINIC_VAL32(Intr_TxDMA,     5, 1) // tx dma completed w/ interrupt
+__SINIC_VAL32(Intr_TxPacket,  4, 1) // packet transmitted
+__SINIC_VAL32(Intr_RxHigh,    3, 1) // rx fifo above high watermark
+__SINIC_VAL32(Intr_RxEmpty,   2, 1) // rx fifo empty
+__SINIC_VAL32(Intr_RxDMA,     1, 1) // rx dma completed w/ interrupt
+__SINIC_VAL32(Intr_RxPacket,  0, 1) // packet received
+__SINIC_REG32(Intr_All,       0x01ff) // all valid interrupts
+__SINIC_REG32(Intr_NoDelay,   0x01cc) // interrupts that aren't coalesced
+__SINIC_REG32(Intr_Res,      ~0x01ff) // reserved interrupt bits
 
 // RX Data Description
-__SINIC_VAL64(RxData_NoDelay,  61,  1); // Don't Delay this copy
-__SINIC_VAL64(RxData_Vaddr,    60,  1); // Addr is virtual
-__SINIC_VAL64(RxData_Len,      40, 20); // 0 - 256k
-__SINIC_VAL64(RxData_Addr,      0, 40); // Address 1TB
+__SINIC_VAL64(RxData_NoDelay,  61,  1) // Don't Delay this copy
+__SINIC_VAL64(RxData_Vaddr,    60,  1) // Addr is virtual
+__SINIC_VAL64(RxData_Len,      40, 20) // 0 - 256k
+__SINIC_VAL64(RxData_Addr,      0, 40) // Address 1TB
 
 // TX Data Description
-__SINIC_VAL64(TxData_More,     63,  1); // Packet not complete (will dma more)
-__SINIC_VAL64(TxData_Checksum, 62,  1); // do checksum
-__SINIC_VAL64(TxData_Vaddr,    60,  1); // Addr is virtual
-__SINIC_VAL64(TxData_Len,      40, 20); // 0 - 256k
-__SINIC_VAL64(TxData_Addr,      0, 40); // Address 1TB
+__SINIC_VAL64(TxData_More,     63,  1) // Packet not complete (will dma more)
+__SINIC_VAL64(TxData_Checksum, 62,  1) // do checksum
+__SINIC_VAL64(TxData_Vaddr,    60,  1) // Addr is virtual
+__SINIC_VAL64(TxData_Len,      40, 20) // 0 - 256k
+__SINIC_VAL64(TxData_Addr,      0, 40) // Address 1TB
 
 // RX Done/Busy Information
-__SINIC_VAL64(RxDone_Packets,   32, 16); // number of packets in rx fifo
-__SINIC_VAL64(RxDone_Busy,      31,  1); // receive dma busy copying
-__SINIC_VAL64(RxDone_Complete,  30,  1); // valid data (packet complete)
-__SINIC_VAL64(RxDone_More,      29,  1); // Packet has more data (dma again)
-__SINIC_VAL64(RxDone_Empty,     28,  1); // rx fifo is empty
-__SINIC_VAL64(RxDone_High,      27,  1); // rx fifo is above the watermark
-__SINIC_VAL64(RxDone_NotHigh,   26,  1); // rxfifo never hit the high watermark
-__SINIC_VAL64(RxDone_TcpError,  25,  1); // TCP packet error (bad checksum)
-__SINIC_VAL64(RxDone_UdpError,  24,  1); // UDP packet error (bad checksum)
-__SINIC_VAL64(RxDone_IpError,   23,  1); // IP packet error (bad checksum)
-__SINIC_VAL64(RxDone_TcpPacket, 22,  1); // this is a TCP packet
-__SINIC_VAL64(RxDone_UdpPacket, 21,  1); // this is a UDP packet
-__SINIC_VAL64(RxDone_IpPacket,  20,  1); // this is an IP packet
-__SINIC_VAL64(RxDone_CopyLen,    0, 20); // up to 256k
+__SINIC_VAL64(RxDone_Packets,   32, 16) // number of packets in rx fifo
+__SINIC_VAL64(RxDone_Busy,      31,  1) // receive dma busy copying
+__SINIC_VAL64(RxDone_Complete,  30,  1) // valid data (packet complete)
+__SINIC_VAL64(RxDone_More,      29,  1) // Packet has more data (dma again)
+__SINIC_VAL64(RxDone_Empty,     28,  1) // rx fifo is empty
+__SINIC_VAL64(RxDone_High,      27,  1) // rx fifo is above the watermark
+__SINIC_VAL64(RxDone_NotHigh,   26,  1) // rxfifo never hit the high watermark
+__SINIC_VAL64(RxDone_TcpError,  25,  1) // TCP packet error (bad checksum)
+__SINIC_VAL64(RxDone_UdpError,  24,  1) // UDP packet error (bad checksum)
+__SINIC_VAL64(RxDone_IpError,   23,  1) // IP packet error (bad checksum)
+__SINIC_VAL64(RxDone_TcpPacket, 22,  1) // this is a TCP packet
+__SINIC_VAL64(RxDone_UdpPacket, 21,  1) // this is a UDP packet
+__SINIC_VAL64(RxDone_IpPacket,  20,  1) // this is an IP packet
+__SINIC_VAL64(RxDone_CopyLen,    0, 20) // up to 256k
 
 // TX Done/Busy Information
-__SINIC_VAL64(TxDone_Packets,   32, 16); // number of packets in tx fifo
-__SINIC_VAL64(TxDone_Busy,      31,  1); // transmit dma busy copying
-__SINIC_VAL64(TxDone_Complete,  30,  1); // valid data (packet complete)
-__SINIC_VAL64(TxDone_Full,      29,  1); // tx fifo is full
-__SINIC_VAL64(TxDone_Low,       28,  1); // tx fifo is below the watermark
-__SINIC_VAL64(TxDone_Res0,      27,  1); // reserved
-__SINIC_VAL64(TxDone_Res1,      26,  1); // reserved
-__SINIC_VAL64(TxDone_Res2,      25,  1); // reserved
-__SINIC_VAL64(TxDone_Res3,      24,  1); // reserved
-__SINIC_VAL64(TxDone_Res4,      23,  1); // reserved
-__SINIC_VAL64(TxDone_Res5,      22,  1); // reserved
-__SINIC_VAL64(TxDone_Res6,      21,  1); // reserved
-__SINIC_VAL64(TxDone_Res7,      20,  1); // reserved
-__SINIC_VAL64(TxDone_CopyLen,    0, 20); // up to 256k
-
-__SINIC_VAL64(RxStatus_Dirty,   48, 16);
-__SINIC_VAL64(RxStatus_Mapped,  32, 16);
-__SINIC_VAL64(RxStatus_Busy,    16, 16);
-__SINIC_VAL64(RxStatus_Head,     0, 16);
+__SINIC_VAL64(TxDone_Packets,   32, 16) // number of packets in tx fifo
+__SINIC_VAL64(TxDone_Busy,      31,  1) // transmit dma busy copying
+__SINIC_VAL64(TxDone_Complete,  30,  1) // valid data (packet complete)
+__SINIC_VAL64(TxDone_Full,      29,  1) // tx fifo is full
+__SINIC_VAL64(TxDone_Low,       28,  1) // tx fifo is below the watermark
+__SINIC_VAL64(TxDone_Res0,      27,  1) // reserved
+__SINIC_VAL64(TxDone_Res1,      26,  1) // reserved
+__SINIC_VAL64(TxDone_Res2,      25,  1) // reserved
+__SINIC_VAL64(TxDone_Res3,      24,  1) // reserved
+__SINIC_VAL64(TxDone_Res4,      23,  1) // reserved
+__SINIC_VAL64(TxDone_Res5,      22,  1) // reserved
+__SINIC_VAL64(TxDone_Res6,      21,  1) // reserved
+__SINIC_VAL64(TxDone_Res7,      20,  1) // reserved
+__SINIC_VAL64(TxDone_CopyLen,    0, 20) // up to 256k
+
+__SINIC_VAL64(RxStatus_Dirty,   48, 16)
+__SINIC_VAL64(RxStatus_Mapped,  32, 16)
+__SINIC_VAL64(RxStatus_Busy,    16, 16)
+__SINIC_VAL64(RxStatus_Head,     0, 16)
 
 struct Info
 {