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authorAndreas Hansson <andreas.hansson@arm.com>2013-07-18 08:31:16 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-07-18 08:31:16 -0400
commitd4273cc9a6f3c00566e97ebcd71509ed14477b37 (patch)
tree9b50625fc5d2bb457a959f379a45687903660237 /src/dev
parent4e8ecd7c6fd0447f563179b5a8fdbb13b562ca9e (diff)
downloadgem5-d4273cc9a6f3c00566e97ebcd71509ed14477b37.tar.xz
mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly.
Diffstat (limited to 'src/dev')
-rw-r--r--src/dev/dma_device.cc2
-rw-r--r--src/dev/dma_device.hh6
2 files changed, 4 insertions, 4 deletions
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index f25f52334..5eb5e1f9d 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -163,7 +163,7 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
event ? event->scheduled() : -1);
- for (ChunkGenerator gen(addr, size, peerBlockSize());
+ for (ChunkGenerator gen(addr, size, sys->cacheLineSize());
!gen.done(); gen.next()) {
Request *req = new Request(gen.addr(), gen.size(), flag, masterId);
PacketPtr pkt = new Packet(req, cmd);
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 3b4bb522d..d1245b977 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -49,6 +49,7 @@
#include "dev/io_device.hh"
#include "params/DmaDevice.hh"
#include "sim/drain.hh"
+#include "sim/system.hh"
class DmaPort : public MasterPort
{
@@ -146,7 +147,6 @@ class DmaPort : public MasterPort
bool dmaPending() const { return pendingCount > 0; }
- unsigned cacheBlockSize() const { return peerBlockSize(); }
unsigned int drain(DrainManager *drainManger);
};
@@ -178,7 +178,7 @@ class DmaDevice : public PioDevice
unsigned int drain(DrainManager *drainManger);
- unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); }
+ unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
virtual BaseMasterPort &getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID);