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authorAndreas Hansson <andreas.hansson@arm.com>2012-08-21 05:49:01 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-08-21 05:49:01 -0400
commit452217817f421a64bc022a5977e795229af45b30 (patch)
tree8f66c1802e5e22cfd4eee963d3cda37b77c5ca08 /src/dev
parent4ebefc145adf818f8695c36a36daacca99f59eb8 (diff)
downloadgem5-452217817f421a64bc022a5977e795229af45b30.tar.xz
Clock: Move the clock and related functions to ClockedObject
This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
Diffstat (limited to 'src/dev')
-rw-r--r--src/dev/CopyEngine.py4
-rw-r--r--src/dev/Ethernet.py6
-rw-r--r--src/dev/arm/RealView.py6
-rw-r--r--src/dev/arm/pl111.cc24
-rw-r--r--src/dev/arm/pl111.hh7
-rw-r--r--src/dev/arm/timer_cpulocal.cc4
-rw-r--r--src/dev/i8254xGBe.cc2
-rw-r--r--src/dev/i8254xGBe.hh2
-rw-r--r--src/dev/ns_gige.cc1
-rw-r--r--src/dev/ns_gige.hh4
-rw-r--r--src/dev/sinic.cc2
-rw-r--r--src/dev/sinic.hh2
12 files changed, 14 insertions, 50 deletions
diff --git a/src/dev/CopyEngine.py b/src/dev/CopyEngine.py
index b89486be8..9aa0e1fe5 100644
--- a/src/dev/CopyEngine.py
+++ b/src/dev/CopyEngine.py
@@ -52,8 +52,8 @@ class CopyEngine(PciDevice):
ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
-
- clock = Param.Clock('500MHz', "Clock speed of the device")
+ # Override the default clock
+ clock = '500MHz'
latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index 91d4e230e..1afbce8ee 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -79,7 +79,8 @@ class IGbE(EtherDevice):
"Number of enteries in the rx descriptor cache")
tx_desc_cache_size = Param.Int(64,
"Number of enteries in the rx descriptor cache")
- clock = Param.Clock('500MHz', "Clock speed of the device")
+ # Override the default clock
+ clock = '500MHz'
VendorID = 0x8086
SubsystemID = 0x1008
SubsystemVendorID = 0x8086
@@ -127,7 +128,8 @@ class EtherDevBase(EtherDevice):
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
- clock = Param.Clock('0ns', "State machine processor frequency")
+ # Override the default clock
+ clock = '0ns'
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 967267197..876188c12 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -118,7 +118,8 @@ class CpuLocalTimer(BasicPioDevice):
gic = Param.Gic(Parent.any, "Gic to use for interrupting")
int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
- clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
+ # Override the default clock
+ clock = '1GHz'
class PL031(AmbaIntDevice):
type = 'PL031'
@@ -134,7 +135,8 @@ class Pl050(AmbaIntDevice):
class Pl111(AmbaDmaDevice):
type = 'Pl111'
- clock = Param.Clock('24MHz', "Clock speed of the input")
+ # Override the default clock
+ clock = '24MHz'
vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
amba_id = 0x00141111
diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index 998644a8c..d79a1cf39 100644
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -63,7 +63,7 @@ Pl111::Pl111(const Params *p)
lcdRis(0), lcdMis(0),
clcdCrsrCtrl(0), clcdCrsrConfig(0), clcdCrsrPalette0(0),
clcdCrsrPalette1(0), clcdCrsrXY(0), clcdCrsrClip(0), clcdCrsrImsc(0),
- clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0), clock(p->clock),
+ clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0),
vncserver(p->vnc), bmp(NULL), width(LcdMaxWidth), height(LcdMaxHeight),
bytesPerPixel(4), startTime(0), startAddr(0), maxAddr(0), curAddr(0),
waterMark(0), dmaPendingNum(0), readEvent(this), fillFifoEvent(this),
@@ -512,26 +512,6 @@ Pl111::dmaDone()
schedule(fillFifoEvent, nextCycle());
}
-
-Tick
-Pl111::nextCycle()
-{
- Tick nextTick = curTick() + clock - 1;
- nextTick -= nextTick%clock;
- return nextTick;
-}
-
-Tick
-Pl111::nextCycle(Tick beginTick)
-{
- Tick nextTick = beginTick;
- if (nextTick%clock!=0)
- nextTick = nextTick - (nextTick%clock) + clock;
-
- assert(nextTick >= curTick());
- return nextTick;
-}
-
void
Pl111::serialize(std::ostream &os)
{
@@ -586,7 +566,6 @@ Pl111::serialize(std::ostream &os)
uint8_t clcdCrsrMis_serial = clcdCrsrMis;
SERIALIZE_SCALAR(clcdCrsrMis_serial);
- SERIALIZE_SCALAR(clock);
SERIALIZE_SCALAR(height);
SERIALIZE_SCALAR(width);
SERIALIZE_SCALAR(bytesPerPixel);
@@ -689,7 +668,6 @@ Pl111::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(clcdCrsrMis_serial);
clcdCrsrMis = clcdCrsrMis_serial;
- UNSERIALIZE_SCALAR(clock);
UNSERIALIZE_SCALAR(height);
UNSERIALIZE_SCALAR(width);
UNSERIALIZE_SCALAR(bytesPerPixel);
diff --git a/src/dev/arm/pl111.hh b/src/dev/arm/pl111.hh
index c4fb84efa..599d4fa3e 100644
--- a/src/dev/arm/pl111.hh
+++ b/src/dev/arm/pl111.hh
@@ -228,9 +228,6 @@ class Pl111: public AmbaDmaDevice
/** Cursor masked interrupt status register - const */
InterruptReg clcdCrsrMis;
- /** Clock speed */
- Tick clock;
-
/** VNC server */
VncServer *vncserver;
@@ -291,10 +288,6 @@ class Pl111: public AmbaDmaDevice
/** DMA done event */
void dmaDone();
- /** Next cycle event */
- Tick nextCycle();
- Tick nextCycle(Tick beginTick);
-
/** DMA framebuffer read event */
EventWrapper<Pl111, &Pl111::readFramebuffer> readEvent;
diff --git a/src/dev/arm/timer_cpulocal.cc b/src/dev/arm/timer_cpulocal.cc
index 97d3c5883..097c52186 100644
--- a/src/dev/arm/timer_cpulocal.cc
+++ b/src/dev/arm/timer_cpulocal.cc
@@ -58,7 +58,7 @@ CpuLocalTimer::CpuLocalTimer(Params *p)
localTimer[i].parent = this;
localTimer[i].intNumTimer = p->int_num_timer;
localTimer[i].intNumWatchdog = p->int_num_watchdog;
- localTimer[i].clock = p->clock;
+ localTimer[i].clock = clock;
localTimer[i].cpuNum = i;
}
pioSize = 0x38;
@@ -339,7 +339,6 @@ CpuLocalTimer::Timer::serialize(std::ostream &os)
DPRINTF(Checkpoint, "Serializing Arm CpuLocalTimer\n");
SERIALIZE_SCALAR(intNumTimer);
SERIALIZE_SCALAR(intNumWatchdog);
- SERIALIZE_SCALAR(clock);
uint32_t timer_control_serial = timerControl;
uint32_t watchdog_control_serial = watchdogControl;
@@ -379,7 +378,6 @@ CpuLocalTimer::Timer::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(intNumTimer);
UNSERIALIZE_SCALAR(intNumWatchdog);
- UNSERIALIZE_SCALAR(clock);
uint32_t timer_control_serial;
UNSERIALIZE_SCALAR(timer_control_serial);
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 14d767288..f7f6a1178 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -68,7 +68,7 @@ IGbE::IGbE(const Params *p)
tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size),
- clock(p->clock), lastInterrupt(0)
+ lastInterrupt(0)
{
etherInt = new IGbEInt(name() + ".int", this);
diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh
index a6b20a2bf..099cd0d11 100644
--- a/src/dev/i8254xGBe.hh
+++ b/src/dev/i8254xGBe.hh
@@ -523,9 +523,7 @@ class IGbE : public EtherDevice
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
- Tick clock;
Tick lastInterrupt;
- inline Tick ticks(int numCycles) const { return numCycles * clock; }
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index 4a459c6c6..6a55516c5 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -99,7 +99,6 @@ NSGigE::NSGigE(Params *p)
txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
txXferLen(0), rxXferLen(0), rxDmaFree(false), txDmaFree(false),
- clock(p->clock),
txState(txIdle), txEnable(false), CTDD(false), txHalt(false),
txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
rxEnable(false), CRDD(false), rxPktBytes(0), rxHalt(false),
diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh
index 87cf56962..8032c0623 100644
--- a/src/dev/ns_gige.hh
+++ b/src/dev/ns_gige.hh
@@ -196,10 +196,6 @@ class NSGigE : public EtherDevice
ns_desc64 txDesc64;
ns_desc64 rxDesc64;
- /* state machine cycle time */
- Tick clock;
- inline Tick ticks(int numCycles) const { return numCycles * clock; }
-
/* tx State Machine */
TxState txState;
bool txEnable;
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index 1030e1a9c..623dcf2c1 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -78,7 +78,7 @@ const char *TxStateStrings[] =
// Sinic PCI Device
//
Base::Base(const Params *p)
- : PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
+ : PciDev(p), rxEnable(false), txEnable(false),
intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
cpuPendingIntr(false), intrEvent(0), interface(NULL)
{
diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh
index 0da7ccae4..5532650c3 100644
--- a/src/dev/sinic.hh
+++ b/src/dev/sinic.hh
@@ -50,8 +50,6 @@ class Base : public PciDev
protected:
bool rxEnable;
bool txEnable;
- Tick clock;
- inline Tick ticks(int numCycles) const { return numCycles * clock; }
protected:
Tick intrDelay;