misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
  case statments. C++17 adds the [[fallthrough]]; declaration. However,
  to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
  M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
  if that doesn't exist, it defaults to nothing (no older compilers
  generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
  in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>

5 files changed, 10 insertions, 8 deletions

diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 350867488..f8433bd2d 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -385,7 +385,7 @@ GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
       case MISCREG_CNTPS_CVAL_EL1:
       case MISCREG_CNTPS_TVAL_EL1:
       case MISCREG_CNTPS_CTL_EL1:
-        /* FALLTHROUGH */
+        M5_FALLTHROUGH;
 
       // PL2 phys. timer, non-secure
       case MISCREG_CNTHCTL:
@@ -466,7 +466,7 @@ GenericTimer::readMiscReg(int reg, unsigned cpu)
       case MISCREG_CNTPS_CVAL_EL1:
       case MISCREG_CNTPS_TVAL_EL1:
       case MISCREG_CNTPS_CTL_EL1:
-        /* FALLTHROUGH */
+        M5_FALLTHROUGH;
 
       // PL2 phys. timer, non-secure
       case MISCREG_CNTHCTL:
diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 3dde72ac7..3359b0d61 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -2290,14 +2290,13 @@ IGbE::rxStateMachine()
         int descLeft = rxDescCache.descLeft();
         DPRINTF(EthernetSM, "RXS: descLeft: %d rdmts: %d rdlen: %d\n",
                 descLeft, regs.rctl.rdmts(), regs.rdlen());
-        switch (regs.rctl.rdmts()) {
-          case 2: if (descLeft > .125 * regs.rdlen()) break;
-          case 1: if (descLeft > .250 * regs.rdlen()) break;
-          case 0: if (descLeft > .500 * regs.rdlen())  break;
+
+        // rdmts 2->1/8, 1->1/4, 0->1/2
+        int ratio = (1ULL << (regs.rctl.rdmts() + 1));
+        if (descLeft * ratio <= regs.rdlen()) {
             DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) "
                     "because of descriptors left\n");
             postInterrupt(IT_RXDMT);
-            break;
         }
 
         if (rxFifo.empty())
diff --git a/src/dev/pci/copy_engine.cc b/src/dev/pci/copy_engine.cc
index 3c7df7d3a..7c87da1c0 100644
--- a/src/dev/pci/copy_engine.cc
+++ b/src/dev/pci/copy_engine.cc
@@ -249,7 +249,7 @@ CopyEngine::CopyEngineChannel::channelRead(Packet *pkt, Addr daddr, int size)
         break;
       case CHAN_STATUS:
         assert(size == sizeof(uint64_t));
-        pkt->set<uint64_t>(cr.status() | ~busy);
+        pkt->set<uint64_t>(cr.status() | (busy ? 0 : 1));
         break;
       case CHAN_CHAINADDR:
         assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
diff --git a/src/dev/storage/ide_disk.cc b/src/dev/storage/ide_disk.cc
index 08d374fa3..020e4582d 100644
--- a/src/dev/storage/ide_disk.cc
+++ b/src/dev/storage/ide_disk.cc
@@ -705,6 +705,7 @@ IdeDisk::startCommand()
         // Supported DMA commands
       case WDCC_WRITEDMA:
         dmaRead = true;  // a write to the disk is a DMA read from memory
+        M5_FALLTHROUGH;
       case WDCC_READDMA:
         if (!(cmdReg.drive & DRIVE_LBA_BIT))
             panic("Attempt to perform CHS access, only supports LBA\n");
diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index 39b02055b..c5fca1b47 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -455,10 +455,12 @@ X86ISA::I8042::write(PacketPtr pkt)
           case WriteOutputPort:
             warn("i8042 \"Write output port\" command not implemented.\n");
             lastCommand = WriteOutputPort;
+            break;
           case WriteKeyboardOutputBuff:
             warn("i8042 \"Write keyboard output buffer\" "
                     "command not implemented.\n");
             lastCommand = WriteKeyboardOutputBuff;
+            break;
           case WriteMouseOutputBuff:
             DPRINTF(I8042, "Got command to write to mouse output buffer.\n");
             lastCommand = WriteMouseOutputBuff;