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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:53:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:53:54 -0400 |
| commit | 88aa7755f4f4ebd39a26fbece9c0d09cd195a010 (patch) | |
| tree | ff24a9bb88a3cf810f3ffd40927290833879bdaa /src/dev | |
| parent | cc8911261e11d67f2b8745289ed5ecbb89c9d917 (diff) | |
| download | gem5-88aa7755f4f4ebd39a26fbece9c0d09cd195a010.tar.xz | |
mem: Avoid explicitly zeroing the memory backing store
This patch removes the explicit memset as it is redundant and causes
the simulator to touch the entire space, forcing the host system to
allocate the pages.
Anonymous pages are mapped on the first access, and the page-fault
handler is responsible for zeroing them. Thus, the pages are still
zeroed, but we avoid touching the entire allocated space which enables
us to use much larger memory sizes as long as not all the memory is
actually used.
Diffstat (limited to 'src/dev')
| -rw-r--r-- | src/dev/arm/RealView.py | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index b5d41ce93..ab994b6f0 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -162,8 +162,7 @@ class RealView(Platform): def setupBootLoader(self, mem_bus, cur_sys, loc): self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), - size = '64MB'), - zero = True) + size = '64MB')) self.nvmem.port = mem_bus.master cur_sys.boot_loader = loc('boot.arm') @@ -360,8 +359,7 @@ class VExpress_EMM(RealView): InterruptLine=2, InterruptPin=2) - vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), - zero = True) + vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB')) rtc = PL031(pio_addr=0x1C170000, int_num=36) l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) @@ -376,8 +374,7 @@ class VExpress_EMM(RealView): mmc_fake = AmbaFake(pio_addr=0x1c050000) def setupBootLoader(self, mem_bus, cur_sys, loc): - self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'), - zero = True) + self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) self.nvmem.port = mem_bus.master cur_sys.boot_loader = loc('boot_emm.arm') cur_sys.atags_addr = 0x80000100 |