diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-07-18 16:53:18 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-08-21 17:20:10 +0000 |
| commit | d84a0714220ffcc10eed0530ec01ed1a01a4ad4b (patch) | |
| tree | 2de78a70847c0ff77ea3aa367ef9bf82afbc6e90 /src/dev | |
| parent | 4fdfd98230e780aeb068e3740742c7bff28fb859 (diff) | |
| download | gem5-d84a0714220ffcc10eed0530ec01ed1a01a4ad4b.tar.xz | |
dev, arm: Fix incorrect GIC address range sizes
The GICv2 specifies that 8KiB of the memory map is allocated to the
CPU interface and 4KiB is allocated to the distributor. The current
distributor size is off by 1 and the CPU interface is completely off
by a lot.
Change-Id: I90a9f669a46a37d79c6cc542087cf91f2044f104
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11769
Diffstat (limited to 'src/dev')
| -rw-r--r-- | src/dev/arm/RealView.py | 2 | ||||
| -rw-r--r-- | src/dev/arm/gic_pl390.hh | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 60b678080..837f79849 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -1052,7 +1052,7 @@ Memory map: 0x2b000000-0x2b00ffff: HDLCD 0x2c001000-0x2c001fff: GIC (distributor) - 0x2c002000-0x2c0020ff: GIC (CPU interface) + 0x2c002000-0x2c003fff: GIC (CPU interface) 0x2c004000-0x2c005fff: vGIC (HV) 0x2c006000-0x2c007fff: vGIC (VCPU) 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh index b4e880bf2..7fd4bcbda 100644 --- a/src/dev/arm/gic_pl390.hh +++ b/src/dev/arm/gic_pl390.hh @@ -72,7 +72,7 @@ class Pl390 : public BaseGic, public BaseGicRegisters GICD_PIDR2 = 0xfe8, // distributor peripheral ID2 GICD_PIDR3 = 0xfec, // distributor peripheral ID3 - DIST_SIZE = 0xfff + DIST_SIZE = 0x1000, }; /** @@ -111,7 +111,7 @@ class Pl390 : public BaseGic, public BaseGicRegisters GICC_APR3 = 0xdc, // active priority register 3 GICC_IIDR = 0xfc, // cpu interface id register - CPU_SIZE = 0xff + CPU_SIZE = 0x2000, }; static const int SGI_MAX = 16; // Number of Software Gen Interrupts |