diff options
author | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 15:48:12 -0600 |
---|---|---|
committer | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 15:48:12 -0600 |
commit | 279f179babc9e5663156777c533c06edc91bce9a (patch) | |
tree | e6718ee514cc81678491b50562ce8c463c0b20fd /src/dev | |
parent | 5aa104e072eb20f6aca49b169521b0c2da33c844 (diff) | |
parent | 295516a590b6e47c9a881f193027447e500c749c (diff) | |
download | gem5-279f179babc9e5663156777c533c06edc91bce9a.tar.xz |
merge
Diffstat (limited to 'src/dev')
-rw-r--r-- | src/dev/Uart.py | 1 | ||||
-rw-r--r-- | src/dev/alpha/tsunami.cc | 1 | ||||
-rw-r--r-- | src/dev/alpha/tsunami_cchip.cc | 1 | ||||
-rw-r--r-- | src/dev/alpha/tsunami_io.cc | 1 | ||||
-rw-r--r-- | src/dev/alpha/tsunami_pchip.cc | 1 | ||||
-rw-r--r-- | src/dev/arm/SConscript | 36 | ||||
-rw-r--r-- | src/dev/arm/Versatile.py | 51 | ||||
-rw-r--r-- | src/dev/arm/versatile.cc | 122 | ||||
-rw-r--r-- | src/dev/arm/versatile.hh | 108 | ||||
-rw-r--r-- | src/dev/baddev.cc | 1 | ||||
-rw-r--r-- | src/dev/ide_ctrl.cc | 2 | ||||
-rw-r--r-- | src/dev/ide_disk.cc | 1 | ||||
-rw-r--r-- | src/dev/mc146818.cc | 24 | ||||
-rwxr-xr-x | src/dev/mips/malta.cc | 2 | ||||
-rwxr-xr-x | src/dev/mips/malta_cchip.cc | 3 | ||||
-rwxr-xr-x | src/dev/mips/malta_io.cc | 1 | ||||
-rwxr-xr-x | src/dev/mips/malta_pchip.cc | 1 | ||||
-rw-r--r-- | src/dev/ns_gige.cc | 1 | ||||
-rw-r--r-- | src/dev/platform.cc | 1 | ||||
-rw-r--r-- | src/dev/sinic.cc | 1 | ||||
-rw-r--r-- | src/dev/sparc/dtod.cc | 1 | ||||
-rw-r--r-- | src/dev/sparc/iob.cc | 14 | ||||
-rw-r--r-- | src/dev/sparc/t1000.cc | 1 | ||||
-rw-r--r-- | src/dev/uart8250.cc | 1 | ||||
-rw-r--r-- | src/dev/x86/i82094aa.cc | 2 | ||||
-rw-r--r-- | src/dev/x86/pc.cc | 1 |
26 files changed, 362 insertions, 18 deletions
diff --git a/src/dev/Uart.py b/src/dev/Uart.py index 5135a064d..9254dc695 100644 --- a/src/dev/Uart.py +++ b/src/dev/Uart.py @@ -28,7 +28,6 @@ from m5.params import * from m5.proxy import * -from m5 import build_env from Device import BasicPioDevice class Uart(BasicPioDevice): diff --git a/src/dev/alpha/tsunami.cc b/src/dev/alpha/tsunami.cc index b6478fe22..b36b5977d 100644 --- a/src/dev/alpha/tsunami.cc +++ b/src/dev/alpha/tsunami.cc @@ -36,6 +36,7 @@ #include <string> #include <vector> +#include "config/the_isa.hh" #include "cpu/intr_control.hh" #include "dev/alpha/tsunami_cchip.hh" #include "dev/alpha/tsunami_pchip.hh" diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc index 52a2aea14..fd76fd93e 100644 --- a/src/dev/alpha/tsunami_cchip.cc +++ b/src/dev/alpha/tsunami_cchip.cc @@ -39,6 +39,7 @@ #include "arch/alpha/ev5.hh" #include "base/trace.hh" +#include "config/the_isa.hh" #include "cpu/intr_control.hh" #include "cpu/thread_context.hh" #include "dev/alpha/tsunami.hh" diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc index 9c88904e3..8b06f5170 100644 --- a/src/dev/alpha/tsunami_io.cc +++ b/src/dev/alpha/tsunami_io.cc @@ -42,6 +42,7 @@ #include "base/time.hh" #include "base/trace.hh" +#include "config/the_isa.hh" #include "dev/rtcreg.h" #include "dev/alpha/tsunami_cchip.hh" #include "dev/alpha/tsunami.hh" diff --git a/src/dev/alpha/tsunami_pchip.cc b/src/dev/alpha/tsunami_pchip.cc index 4df7d1150..df980cf79 100644 --- a/src/dev/alpha/tsunami_pchip.cc +++ b/src/dev/alpha/tsunami_pchip.cc @@ -38,6 +38,7 @@ #include <vector> #include "base/trace.hh" +#include "config/the_isa.hh" #include "dev/alpha/tsunami_pchip.hh" #include "dev/alpha/tsunamireg.h" #include "dev/alpha/tsunami.hh" diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript new file mode 100644 index 000000000..dd1d73e1a --- /dev/null +++ b/src/dev/arm/SConscript @@ -0,0 +1,36 @@ +# -*- mode:python -*- + +# Copyright (c) 2009 ARM Limited +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +Import('*') + +if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm': + SimObject('Versatile.py') + + Source('versatile.cc') diff --git a/src/dev/arm/Versatile.py b/src/dev/arm/Versatile.py new file mode 100644 index 000000000..7f36bbcf3 --- /dev/null +++ b/src/dev/arm/Versatile.py @@ -0,0 +1,51 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2009 ARM Limited +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.params import * +from m5.proxy import * +from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr +from Platform import Platform +from Terminal import Terminal +from Uart import Uart8250 + + +class Versatile(Platform): + type = 'Versatile' + system = Param.System(Parent.any, "system") + + # Attach I/O devices that are on chip + def attachOnChipIO(self, bus): + pass + + + # Attach I/O devices to specified bus object. Can't do this + # earlier, since the bus object itself is typically defined at the + # System level. + def attachIO(self, bus): + pass diff --git a/src/dev/arm/versatile.cc b/src/dev/arm/versatile.cc new file mode 100644 index 000000000..7d571db99 --- /dev/null +++ b/src/dev/arm/versatile.cc @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * Copyright (c) 2009 ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +/** @file + * Implementation of Versatile platform. + */ + +#include <deque> +#include <string> +#include <vector> + +#include "config/the_isa.hh" +#include "cpu/intr_control.hh" +#include "dev/arm/versatile.hh" +#include "dev/terminal.hh" +#include "sim/system.hh" + +using namespace std; +using namespace TheISA; + +Versatile::Versatile(const Params *p) + : Platform(p), system(p->system) +{ + // set the back pointer from the system to myself + system->platform = this; +} + +Tick +Versatile::intrFrequency() +{ + panic("Need implementation\n"); + M5_DUMMY_RETURN +} + +void +Versatile::postConsoleInt() +{ + warn_once("Don't know what interrupt to post for console.\n"); + //panic("Need implementation\n"); +} + +void +Versatile::clearConsoleInt() +{ + warn_once("Don't know what interrupt to clear for console.\n"); + //panic("Need implementation\n"); +} + +void +Versatile::postPciInt(int line) +{ + panic("Need implementation\n"); +} + +void +Versatile::clearPciInt(int line) +{ + panic("Need implementation\n"); +} + +Addr +Versatile::pciToDma(Addr pciAddr) const +{ + panic("Need implementation\n"); + M5_DUMMY_RETURN +} + + +Addr +Versatile::calcPciConfigAddr(int bus, int dev, int func) +{ + panic("Need implementation\n"); + M5_DUMMY_RETURN +} + +Addr +Versatile::calcPciIOAddr(Addr addr) +{ + panic("Need implementation\n"); + M5_DUMMY_RETURN +} + +Addr +Versatile::calcPciMemAddr(Addr addr) +{ + panic("Need implementation\n"); + M5_DUMMY_RETURN +} + +Versatile * +VersatileParams::create() +{ + return new Versatile(this); +} diff --git a/src/dev/arm/versatile.hh b/src/dev/arm/versatile.hh new file mode 100644 index 000000000..edec3631c --- /dev/null +++ b/src/dev/arm/versatile.hh @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * Copyright (c) 2009 ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +/** + * @file + * Declaration of top level class for the Versatile platform chips. This class just + * retains pointers to all its children so the children can communicate. + */ + +#ifndef __DEV_ARM_VERSATILE_HH__ +#define __DEV_ARM_VERSATILE_HH__ + +#include "dev/platform.hh" +#include "params/Versatile.hh" + +class IdeController; +class System; + +class Versatile : public Platform +{ + public: + /** Pointer to the system */ + System *system; + + public: + typedef VersatileParams Params; + /** + * Constructor for the Tsunami Class. + * @param name name of the object + * @param s system the object belongs to + * @param intctrl pointer to the interrupt controller + */ + Versatile(const Params *p); + + /** + * Return the interrupting frequency to AlphaAccess + * @return frequency of RTC interrupts + */ + virtual Tick intrFrequency(); + + /** + * Cause the cpu to post a serial interrupt to the CPU. + */ + virtual void postConsoleInt(); + + /** + * Clear a posted CPU interrupt + */ + virtual void clearConsoleInt(); + + /** + * Cause the chipset to post a cpi interrupt to the CPU. + */ + virtual void postPciInt(int line); + + /** + * Clear a posted PCI->CPU interrupt + */ + virtual void clearPciInt(int line); + + + virtual Addr pciToDma(Addr pciAddr) const; + + /** + * Calculate the configuration address given a bus/dev/func. + */ + virtual Addr calcPciConfigAddr(int bus, int dev, int func); + + /** + * Calculate the address for an IO location on the PCI bus. + */ + virtual Addr calcPciIOAddr(Addr addr); + + /** + * Calculate the address for a memory location on the PCI bus. + */ + virtual Addr calcPciMemAddr(Addr addr); +}; + +#endif // __DEV_ARM_VERSATILE_HH__ diff --git a/src/dev/baddev.cc b/src/dev/baddev.cc index 6cdee0310..356574c71 100644 --- a/src/dev/baddev.cc +++ b/src/dev/baddev.cc @@ -37,6 +37,7 @@ #include <vector> #include "base/trace.hh" +#include "config/the_isa.hh" #include "dev/baddev.hh" #include "dev/platform.hh" #include "mem/port.hh" diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc index a8cceda1f..87dc0b2aa 100644 --- a/src/dev/ide_ctrl.cc +++ b/src/dev/ide_ctrl.cc @@ -75,8 +75,6 @@ IdeController::Channel::Channel( IdeController::Channel::~Channel() { - delete master; - delete slave; } IdeController::IdeController(Params *p) diff --git a/src/dev/ide_disk.cc b/src/dev/ide_disk.cc index 83faf508e..fe93924f9 100644 --- a/src/dev/ide_disk.cc +++ b/src/dev/ide_disk.cc @@ -39,6 +39,7 @@ #include <string> #include "arch/isa_traits.hh" +#include "config/the_isa.hh" #include "base/chunk_generator.hh" #include "base/cprintf.hh" // csprintf #include "base/trace.hh" diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc index b25b015d2..2e6ed2a4b 100644 --- a/src/dev/mc146818.cc +++ b/src/dev/mc146818.cc @@ -105,6 +105,8 @@ MC146818::MC146818(EventManager *em, const string &n, const struct tm time, MC146818::~MC146818() { + deschedule(tickEvent); + deschedule(event); } void @@ -207,6 +209,15 @@ MC146818::serialize(const string &base, ostream &os) arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data)); paramOut(os, base + ".stat_regA", stat_regA); paramOut(os, base + ".stat_regB", stat_regB); + + // + // save the timer tick and rtc clock tick values to correctly reschedule + // them during unserialize + // + Tick rtcTimerInterruptTickOffset = event.when() - curTick; + SERIALIZE_SCALAR(rtcTimerInterruptTickOffset); + Tick rtcClockTickOffset = event.when() - curTick; + SERIALIZE_SCALAR(rtcClockTickOffset); } void @@ -218,10 +229,15 @@ MC146818::unserialize(const string &base, Checkpoint *cp, paramIn(cp, section, base + ".stat_regA", stat_regA); paramIn(cp, section, base + ".stat_regB", stat_regB); - // We're not unserializing the event here, but we need to - // rescehedule the event since curTick was moved forward by the - // checkpoint - reschedule(event, curTick + event.interval); + // + // properly schedule the timer and rtc clock events + // + Tick rtcTimerInterruptTickOffset; + UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset); + reschedule(event, curTick + rtcTimerInterruptTickOffset); + Tick rtcClockTickOffset; + UNSERIALIZE_SCALAR(rtcClockTickOffset); + reschedule(tickEvent, curTick + rtcClockTickOffset); } MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i) diff --git a/src/dev/mips/malta.cc b/src/dev/mips/malta.cc index 1401fe9ee..73dc9f116 100755 --- a/src/dev/mips/malta.cc +++ b/src/dev/mips/malta.cc @@ -37,6 +37,7 @@ #include <string> #include <vector> +#include "config/the_isa.hh" #include "cpu/intr_control.hh" #include "dev/mips/malta_cchip.hh" #include "dev/mips/malta_pchip.hh" @@ -46,7 +47,6 @@ #include "params/Malta.hh" #include "sim/system.hh" - using namespace std; using namespace TheISA; diff --git a/src/dev/mips/malta_cchip.cc b/src/dev/mips/malta_cchip.cc index 265977665..b2d5069c5 100755 --- a/src/dev/mips/malta_cchip.cc +++ b/src/dev/mips/malta_cchip.cc @@ -39,6 +39,7 @@ #include "arch/mips/mips_core_specific.hh" #include "base/trace.hh" +#include "config/the_isa.hh" #include "cpu/intr_control.hh" #include "cpu/thread_context.hh" #include "dev/mips/malta.hh" @@ -56,7 +57,7 @@ using namespace TheISA; MaltaCChip::MaltaCChip(Params *p) : BasicPioDevice(p), malta(p->malta) { - warn("MaltaCCHIP::MaltaCChip() not implemented."); + warn("MaltaCCHIP::MaltaCChip() not implemented."); pioSize = 0xfffffff; //Put back pointer in malta diff --git a/src/dev/mips/malta_io.cc b/src/dev/mips/malta_io.cc index 7f04789db..5a738a9b4 100755 --- a/src/dev/mips/malta_io.cc +++ b/src/dev/mips/malta_io.cc @@ -42,6 +42,7 @@ #include "base/time.hh" #include "base/trace.hh" +#include "config/the_isa.hh" #include "dev/rtcreg.h" #include "dev/mips/malta_cchip.hh" #include "dev/mips/malta.hh" diff --git a/src/dev/mips/malta_pchip.cc b/src/dev/mips/malta_pchip.cc index b357e3b61..035433021 100755 --- a/src/dev/mips/malta_pchip.cc +++ b/src/dev/mips/malta_pchip.cc @@ -38,6 +38,7 @@ #include <vector> #include "base/trace.hh" +#include "config/the_isa.hh" #include "dev/mips/malta_pchip.hh" #include "dev/mips/maltareg.h" #include "dev/mips/malta.hh" diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 912ca7f0f..86f081ec5 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -39,6 +39,7 @@ #include "base/debug.hh" #include "base/inet.hh" #include "base/types.hh" +#include "config/the_isa.hh" #include "cpu/thread_context.hh" #include "dev/etherlink.hh" #include "dev/ns_gige.hh" diff --git a/src/dev/platform.cc b/src/dev/platform.cc index 2b51a6245..a91a5abf9 100644 --- a/src/dev/platform.cc +++ b/src/dev/platform.cc @@ -30,6 +30,7 @@ */ #include "base/misc.hh" +#include "config/the_isa.hh" #include "dev/platform.hh" #include "sim/sim_exit.hh" diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 133f70b0b..86090e048 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -36,6 +36,7 @@ #include "base/debug.hh" #include "base/inet.hh" #include "base/types.hh" +#include "config/the_isa.hh" #include "cpu/intr_control.hh" #include "cpu/thread_context.hh" #include "dev/etherlink.hh" diff --git a/src/dev/sparc/dtod.cc b/src/dev/sparc/dtod.cc index 81132ac65..c7243cfb8 100644 --- a/src/dev/sparc/dtod.cc +++ b/src/dev/sparc/dtod.cc @@ -39,6 +39,7 @@ #include "base/time.hh" #include "base/trace.hh" +#include "config/the_isa.hh" #include "dev/sparc/dtod.hh" #include "dev/platform.hh" #include "mem/packet_access.hh" diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc index 4543dd07b..40f856d8a 100644 --- a/src/dev/sparc/iob.cc +++ b/src/dev/sparc/iob.cc @@ -90,20 +90,18 @@ void Iob::readIob(PacketPtr pkt) { Addr accessAddr = pkt->getAddr() - iobManAddr; - int index; - uint64_t data; if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) { - index = (accessAddr - IntManAddr) >> 3; - data = intMan[index].cpu << 8 | intMan[index].vector << 0; + int index = (accessAddr - IntManAddr) >> 3; + uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0; pkt->set(data); return; } if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { - index = (accessAddr - IntManAddr) >> 3; - data = intCtl[index].mask ? 1 << 2 : 0 | - intCtl[index].pend ? 1 << 0 : 0; + int index = (accessAddr - IntCtlAddr) >> 3; + uint64_t data = intCtl[index].mask ? 1 << 2 : 0 | + intCtl[index].pend ? 1 << 0 : 0; pkt->set(data); return; } @@ -199,7 +197,7 @@ Iob::writeIob(PacketPtr pkt) } if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { - index = (accessAddr - IntManAddr) >> 3; + index = (accessAddr - IntCtlAddr) >> 3; data = pkt->get<uint64_t>(); intCtl[index].mask = bits(data,2,2); if (bits(data,1,1)) diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc index 88fb358ef..c00d942c9 100644 --- a/src/dev/sparc/t1000.cc +++ b/src/dev/sparc/t1000.cc @@ -36,6 +36,7 @@ #include <string> #include <vector> +#include "config/the_isa.hh" #include "cpu/intr_control.hh" #include "dev/sparc/t1000.hh" #include "dev/terminal.hh" diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc index 93f71f49b..e3eacaaa2 100644 --- a/src/dev/uart8250.cc +++ b/src/dev/uart8250.cc @@ -38,6 +38,7 @@ #include "base/inifile.hh" #include "base/str.hh" // for to_number #include "base/trace.hh" +#include "config/the_isa.hh" #include "dev/platform.hh" #include "dev/terminal.hh" #include "dev/uart8250.hh" diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc index ed936d0cb..591fee6a4 100644 --- a/src/dev/x86/i82094aa.cc +++ b/src/dev/x86/i82094aa.cc @@ -151,7 +151,7 @@ X86ISA::I82094AA::signalInterrupt(int line) DPRINTF(I82094AA, "Entry was masked.\n"); return; } else { - TriggerIntMessage message; + TriggerIntMessage message = 0; message.destination = entry.dest; if (entry.deliveryMode == DeliveryMode::ExtInt) { assert(extIntPic); diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc index 7dc1d8711..e3449abf6 100644 --- a/src/dev/x86/pc.cc +++ b/src/dev/x86/pc.cc @@ -38,6 +38,7 @@ #include "arch/x86/intmessage.hh" #include "arch/x86/x86_traits.hh" +#include "config/the_isa.hh" #include "cpu/intr_control.hh" #include "dev/terminal.hh" #include "dev/x86/i82094aa.hh" |