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author | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-06-04 10:08:21 +0200 |
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committer | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-06-04 10:08:21 +0200 |
commit | a3685b0181ea4a71bd82fea11fa0e6df47b0cd93 (patch) | |
tree | d1cfb2302c424cbef2eb01a16537e4d5d92bfbec /src/dev | |
parent | 7846f59d0dcb36c13e06a3ba8a4c461e646582b6 (diff) | |
download | gem5-a3685b0181ea4a71bd82fea11fa0e6df47b0cd93.tar.xz |
dev: Clarify why updates are delayed when the MC14818 is activated
Diffstat (limited to 'src/dev')
-rw-r--r-- | src/dev/mc146818.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc index abacd8742..81366b774 100644 --- a/src/dev/mc146818.cc +++ b/src/dev/mc146818.cc @@ -163,8 +163,10 @@ MC146818::writeData(const uint8_t addr, const uint8_t data) if (tickEvent.scheduled()) deschedule(tickEvent); } else if (rega_dv_disabled(old_rega)) { - // If the divider chain goes from reset to active, we - // need to schedule a tick after precisely 0.5s. + // According to the specification, the next tick + // happens after 0.5s when the divider chain goes + // from reset to active. So, we simply schedule the + // tick after 0.5s. assert(!tickEvent.scheduled()); schedule(tickEvent, curTick() + SimClock::Int::s / 2); } |